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Intel to describe functional blocks to enable 4.5- and 6-GHz processors
By Semiconductor Business News
June 10, 2002 (5:25 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020609S0003
SANTA CLARA, Calif. -- During the VLSI Circuit Symposium event in Hawaii this week, Intel Corp. will describe some new breakthroughs for next-generation ICs, including some functional blocks to enable 4.5- and 6-GHz microprocessors. In various papers at the event, Intel will describe the development of new, high-speed caches and address generator units for future processors. The company will present details on new, low-power technologies, such as forward body bias. And it will also address the new and emerging problem in chip designs: soft error rates. It will take a combination of new technologies to meet the requirements for future processors, said Shekhar Borkar, an Intel Fellow within the company's R&D arm, Intel Labs. “The biggest challenge is power reduction,†Borkar said. “But there is no single silver bullet,†he told SBN. At present, Intel is shipping chips, based on its new, 0.13-micron process technology. It is expected to roll out 90-nm chips by 2003 and 65-nm designs in 2005, according to Intel's roadmap. By the end of this decade, the company is also expected to develop and ship processors that run at speeds from 10-to-20-GHz. But to enable these high-speed chips, Intel is scrambling to address a major issue: power consumption. If processors continue to use conventional transistors, then future devices could one day dissipate as much power as a nuclear plant--or even the sun's surface, according to Intel. In response, Intel has been devising some new and key transistor-level technologies to reduce power consumption. The company is working on what it calls the TeraHertz transistor, which marks the company's initial use of high-k dielectrics, epitaxial wafers, and a real shocker--silicon-on-insulator (SOI) technology. Intel is also embracing what it calls forward and reverse body bias technology in chip designs. Forward bias enables a 23% reduction in active power in chip designs, while reverse bias cuts stand-by leakage by three-and-a-half times over current technologies, according to Intel. This week, Intel will also move to push the speeds in future chip designs. For example, the company will present a paper that describes a 4.5-GHz address generator unit with a 32-bit sparse-tree adder core. This functional block is based on 0.13-micron technology. It will also describe a 5-GHz integer core, with a dual-supply clocking function, based on 0.13-micron technology. The company will also describe a 6-GHz , 16-KB Level One cache, based on 90-nm technology.