Designed in the Toshiba 90nm Process for Small Silicon Footprint and Reduced Cost; Scalable for More than 64 Ports of Fibre Channel
SAN JOSE, Calif. January 24, 2006 — Toshiba America Electronic Components, Inc. (TAEC)* today announced a new multi-protocol, high-speed SERDES I/O core family of products for 1/2/4 gigabit per second (Gbps) Fibre Channel, 10-gigabit Ethernet, 1.5/3.0Gbps Serial ATA (SATA) and 1.5/3.0Gbps Serial Attached SCSI (SAS) applications. The Fibre Channel PHY cells support implementations of protocol controller, switch and disk drive ICs for such applications as host bus adapters, fabric, director edge and core switches and storage arrays. The core has one of the smallest silicon footprints in the 90 nanometer (nm) process node and is scalable for more than 64 ports of Fibre Channel. This core includes a new rate selectivity feature that allows auto negotiation with uncompromised jitter performance in the system. Other key features include receiver (Rx)/transmitter (Tx) equalization, clock multiplexing and SATA spread spectrum clocking. The cores are currently available for customer design-in.
"Toshiba is committed to providing the silicon-proven, high-speed interfaces required for the custom SoC market and our new multi-protocol, high-speed SERDES I/O core family of products is another step forward," said Dr. Rakesh Sethi, director of business development in the Custom SoC and Foundry Business Unit at TAEC. "We've deployed a single core to address the Fibre Channel, SATA, SAS and chip-to-chip connectivity platforms. Our solution allows integration of multiple cores as high as 128 Rx/Tx on a single chip and uses Toshiba 90nm process technology for low power, reduced cost and one of the smallest 90nm footprints in the industry. We have validated the core on silicon and customer applications ranging from 1/2/4Gbps and SATA Gen1 and Gen2."
The family of products makes optimum form factors achievable, while minimizing power consumption and enabling high-port densities. The cells allow rate selectivity on a per channel basis for mixed systems using 1/2/4Gbps Fibre Channel and 1.5/3.0Gbps SATA/SAS. Dr. Sethi explained that "this rate selectivity feature with intelligent switching results in fewer clock resources on the board and a lower bill of material cost for our customers." The core maintains compatibility to legacy systems as both Rx and Tx can operate at different data rates and can support auto negotiation controlled by a high level. In addition, the core can handle legacy voltage levels up to 2 volts (V) peak-to-peak differential output on the Rx and Tx cells. Both 50 and 75 ohms termination is supported. Tight jitter performance allows for ease of support in SAS and SATA applications.
Main Features
About the 90nm TC300 Family of Custom SoCs
The TC300 family of custom SoCs is designed for applications needing high performance with a small die size. The 90nm custom SoC family employs high-density gates, memories, I/Os and interconnect structures and is well-suited for systems above 300MHz or 5 million gates. Three library options for low power, high speed and very high speed may be mixed and matched in designs to permit optimum performance with a small die size and low power. Toshiba has delivered more than two-dozen 90nm designs in volume production over the last year and over 15 million chips in 90nm since 2004.
Availability
The core is currently available for customer design-in. Volume production is planned to start in the second quarter of 2006. For a product brief, please visit:
http://www.toshiba.com/taec/adinfo/socworld/literature.html.
*About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes memory and flash memory-based storage solutions, a broad range of discrete devices, displays, medical tubes, ASICs, custom SOCs, microprocessors, microcontrollers and wireless components for the computing, wireless, networking, automotive and digital consumer markets.