CAPARICA, Portugal, January 23, 2006 — Acacia Semiconductor today announced it has proved in silicon a 14-bit ADC IP, code-named AS1410aT, targeting communications and consumer applications.
The AS1410aT is a 14-bit ADC operating at 10MS/s over a single 1.8V supply and was implemented in a 0.18µm CMOS process. The ADC core requires no calibration or trimming and occupies a die area of only 1.22mm2. Auxiliary circuits comprising a low-noise bandgap reference and 4 voltage reference buffers are also included to provide a complete ADC solution.
This ADC employs a high-performance front-end input sample-and-hold (S/H) circuit and a differential pipeline architecture with digital error correction.
The S/H features a 2-bit programmable gain allowing a differential input range from 0.5Vpp to 1Vpp, an analog input bandwidth higher than 200MHz and can operate in under-sampling mode for communications applications.
The 14-bit ADC features a DNL and an INL of ±0.7LSB and ±4.0LSB, respectively, measured for typical conditions.
Dynamic performance highlights measured for a 1Vpp differential input signal with 1MHz frequency and 10MS/s sampling rate include an SNR of 65dB, SNDR of 64dB, THD of -73dB and SFDR of 75dB.
The above performance results are achieved with the 14-bit ADC core dissipating less than 14mW over a 1.8V supply.
“We are extremely pleased in having achieved outstanding performance simultaneously across key performance metrics, namely high linearity, ultra-low power, excellent dynamic performance and compact die sizeâ€, said Dr. Bruno Vaz, Team Leader for ADC Design at Acacia Semiconductor.
“Typically, this type of ADC linearity performance is only obtained using well-controlled proprietary analog fabrication processes, trimming steps or complex calibrating circuitryâ€, he continued.
“In our case, we have gone two steps further by minimizing power dissipation and designing this 14-bit ADC in a conventional pure-play foundry process, thereby demonstrating the quality of our design techniques and the effectiveness of our design methodology based on a proprietary analog design optimization and sizing engineâ€, concluded Dr. Vaz.
The AS1410aT can be cost-effectively ported across foundries and process nodes upon request.