SAN JOSE, Calif. — August 8, 2006 — LogicVision, Inc. (NASDAQ: LGVN), a leading provider of semiconductor test and yield learning solutions, today announced a successful collaboration with DA-Test to enable low cost, high accuracy testing of high speed serializer/deserializer (SerDes) circuits. Using LogicVision’s new ETSerdes embedded test Intellectual Property (IP), DA-Test and LogicVision have successfully tested 3.2 Gbps SerDes semiconductor devices on low cost Automatic Test Equipment (ATE) without the need for costly high-speed SerDes instrumentation.
The 2005 International Technology Roadmap for Semiconductors (ITRS) highlighted the dramatic growth in industry use of high-speed SerDes I/O devices, as well as increases in both data rates and lane counts of these devices. The conclusion was a need for low cost parametric test for high performance I/O channels such as PCI-Express, Ethernet, and SATA.
“The semiconductor manufacturers’ concerns with SerDes test are: the high cost of testing, the time it takes to bring these devices to market, and the loss in yield caused by wider design and test guardbands necessitated due to inaccuracies in off-chip instrumentation,†said Farhad Hayat, VP of Marketing at LogicVision. “In response to these concerns, LogicVision has developed the ETSerdes IP solution to enable the testing of any-speed SerDes semiconductor devices on low cost ATE.â€
“We see high demand for test development services for multi-gigabit SerDes devices, and our customers require accurate, robust, low-cost production test technologies,†said Sam Ho, President/CEO at DA-Test. “LogicVision’s ETSerdes IP provides a great cost savings opportunity for semiconductor design teams using SerDes.â€
Using LogicVision’s ETSerdes IP in an off-the-shelf FPGA, DA-Test implemented at-speed I/O tests that measure waveshape, jitter, and jitter tolerance parameters, with production test times. DA-Test was able to measure rise and fall times in the 100 ps range using the ETSerdes offset voltage injection and pulse width measurement technique. HF jitter in the 3~5 ps RMS range was measured within the chip’s receiver using the ETSerdes golden PLL-comparable method, and all tests were measured with sub-picosecond accuracy and repeatability. All test patterns were generated automatically by LogicVison’s ETSerdes application software and DA-Test verified that measurement values could be compared on-chip to shifted-in test limits.
The ETSerdes provides a high accuracy solution that allows testing any SerDes device at any serial data rate on low cost ATE. Additionally, because ETSerdes can be on-chip, it provides this sub-picosecond accuracy at wafer probe, package, board and system test.
Based on the success of this project, DA-Test is now able to provide test development services for low cost testers and multi-gigabit SerDes ICs that incorporate LogicVision’s embedded SerDes test.