Dolphin Integration announces a density record for Dual Port Register Files saving up to 30% of area

Grenoble, France – April 1, 2011. The innovative ERIS architecture for Dual Port Register Files is the attractive alternative to conventional Dual Port memory generators at 130 nm.

The DpRFolderâ„¢ ERIS (2R/2W) allows power and cost reductions, while satisfying the speed constraint of many high-speed applications from high-density consumers and portable devices.

Highlights

Reduced die cost

• Up to 30% denser than older solutions on the market
• Optional High Density BIST for industrial test of instances
• Layout compatibility between various foundries

The easiest integration in your SoC

• All the flexibility of 2 independent read and 2 independent write ports (2R/2W)
• Library of synthesizable models through StorageWareâ„¢ for facilitating the selection and integration of small memories

The Dolphin quality

• Guaranteed design yield for the memories in your circuits

Have a quick look at the Presentation Sheet.

To request an access to the DpRFile ERIS generator, click here

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime