techbullion.com, May. 23, 2025 –
In a significant step toward restoring America’s semiconductor leadership, the U.S. Department of Commerce has announced $1.4 billion in new awards under the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). The goal is to establish a domestic ecosystem where the most advanced chips are designed, fabricated in the United States, and packaged at scale. This shift is crucial for sectors like autonomous vehicles, defence systems, and AI hardware, where every layer of the chip stack must be reliable, secure, and production-ready.
However, while the spotlight often falls on design and computing power, another critical discipline ensures these chips are safe to deploy: Design for Testability (DFT). As chips grow more complex, testing and validation have become technically and geopolitically strategic priorities. To understand what’s changing behind the scenes, we spoke with Vijayaprabhuvel Rajavel, a Technical Architect at HCL America, who leads DFT for custom complex, high-performance ASICs in automotive and intelligent systems. A Senior Member of IEEE, a Fellow of the Soft Computing Research Society, an Exemplary Initiate of Epsilon Pi Tau, and the creator of ExploreDFT, he shares how testability impacts chip trust, safety, and innovation, particularly when lives are at stake.
Vijayaprabhuvel, given the recent CHIPS Act funding, how does DFT factor into this new ecosystem, where design, manufacturing, and packaging are entirely within the U.S.?
The CHIPS Act is reshaping how the U.S. approaches semiconductor development by bringing all primary phases—design, fabrication, and packaging—into a single national framework. Design for Testability becomes essential in that environment to ensure each chip leaving the line is functionally sound, traceable, and production-ready at scale. As advanced packaging techniques, such as chiplets and 3D integration, gain traction, the role of DFT becomes increasingly important. It must account for new interconnect paths, thermal variations, and integration-related failure modes that traditional test flows were not designed to handle. At the IEEE Congressional Visits Day (CVD) 2025 in Washington, D.C., I directly engaged with the Senators, House Representatives, and their staff to discuss technology policies, reinforcing DFT’s critical role in national technology strategies.
DFT also centrally enables data continuity across the manufacturing pipeline. With manufacturing and packaging localised, there’s a greater opportunity to correlate test data with layout, process variations, and system-level behaviour. DFT architectures designed with this in mind can unlock faster yield learning and more effective root-cause analysis, particularly in safety-critical domains such as defence and automotive.
You were Alphawave Semi’s first DFT hire in the U.S., leading the productization of DFT IP and shift-left scan strategies. How do the DFT challenges in complex, high-performance Application Specific Integrated Circuits (ASIC) for chiplets and autonomous systems differ from those in more traditional chip designs?
High-performance ASICs for chiplets and autonomous systems demand greater design flexibility and fault coverage than traditional applications. These chips often integrate a combination of high-speed serial interfaces, dense memory arrays, and real-time processing cores, creating a fragmented landscape for scan insertion and coverage closure. In this environment, design-for-test requires a modular, Shift-left, or RTL-aware approach, where each subsystem is treated with tailored strategies to ensure signal visibility and controllability without compromising performance.
In addition, safety and traceability become critical. Faults must be isolated quickly, sometimes even during deployment, and power constraints during tests are stricter due to thermal and long-term reliability concerns. At Alphawave, the emphasis was building scan architectures that could meet these demands—reusable, scalable, and validated across different designs. As the first DFT engineer on the U.S. team, I ensured that the IP was testable, the methodology was reusable, and ready for seamless integration into advanced silicon.
Testing is often viewed as a final step, but how early should testability be integrated into the design process in high-risk applications such as self-driving vehicles or defense?
In mission-critical applications, testability must be considered from the architecture stage, not after the RTL is frozen. The earlier DFT is part of the design conversation, the more seamlessly it can align with performance, power, and area goals, especially in systems where faults can translate into safety violations. Waiting until the back end often leads to compromises, patchwork fixes, or even redesigns when coverage targets or timing budgets aren’t met.