Jun. 26, 2025 –
In the following article, Tony Chan-Carusone explores the critical role of Forward Error Correction (FEC) in high-speed wireline networking, particularly with the adoption of PAM4 modulation for mid-distance transmission across data centers and how advances in programmable hardware for verification can achieve speeds 10,000 times faster than traditional software-based simulation.
As data transmission rates increase, FEC is essential for maintaining low error rates and obviating the need for retransmission. The performance of modern FEC depends critically on the details of the receiver DSP, particularly with respect to the potential for bursts of errors to corrupt entire frames of data, making them uncorrectable. Software-based time-domain simulation is traditionally used to verify the performance of FEC. However, software simulation is too slow to confirm the probability of these extremely rare error events.
Fortunately, using FPGAs complete links can be modelled and simulated with enough speed and accuracy to validate FEC performance in a wide variety of real application scenarios prior to widespread deployment. Moreover, such a model can be used to evaluate alternative DSP and FEC for new emerging applications. With high-speed networking evolving rapidly, these innovations will be a key focus at OFC, where experts will explore the latest advancements shaping the future of optical and data center connectivity.
In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate requires higher signal bandwidths, with a commensurate increase in the amount of noise in receivers. Thus, more powerful and complex FEC may be expected to counter the increased noise levels.
Next generation PAM4 wireline links for data-centre interconnection will support transmission rates of 200 Gbps per serial lane. The IEEE 802.3dj task force is responsible for writing the standard that implementors will use to develop their 200 Gbps Ethernet interfaces. To prevent a rise in bit error rate (BER), the task force has adopted a two-layer FEC scheme with inner and outer codes to provide two layers of error correction. However, many details of the system-level architecture and how they affect FEC performance need to be analysed...