Dec. 10, 2025 –
Hsinchu, Taiwan – Andes Technology Corporation (TWSE:6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of RISC-V processor cores and the founding member of RISC-V International announces its final database hand-off for the AX46MPV has been made to the first licensee, enabling it to tape-out at TSMC. Several more AX46MPV customers will follow during Q4, 25 and throughout 2026. The third generation vector core, AX46MPV accelerates the pace of Andes success in the cloud AI compute market in the past five years with up to 70% performance improvements in the compute kernels.
“We are heartened by our customer’s tape-out and its performance gain. The timing is just about perfect,” said Dr. Charlie Su, Andes president and CTO. “nVidia’s recent CPX announcement has spotlighted the move away from general purpose GPUs to more power efficient hardware accelerator-based AI infrastructure, complemented by equally efficient CPUs. We are glad to showcase our customer’s success with the AX46MPV to enable this transition.”
Indeed, the Transformer AI models are compute intensive, especially in the “pre-fill” area before tokens are generated (“decode”). Therefore, specialized hardware such as systolic arrays or Compute In Memory (CIM) matrix engines are almost always higher performance and lower power than general purpose GPUs. However, these matrix engines cannot run all Transformer functions, and they need management and support. This is why accelerator chip generally need on-board CPUs in the System-on-Chip (SOC). The NX27V was the first generation Andes RISC-V vector core, being designed into Meta’s MTIA-1 in 2019, dispatching tasks to the accelerator blocks and computing functions that specialized functional blocks are not designed to operate on. The AX45MPV continues to expand Andes business as the cloud AI infrastructure build-out explodes. The AX45MPV beat all other RISC-V competitors Andes customers benchmarked by at least 25% in 2024. The AX46MPV seeks to solidify this leadership by focusing on the Transformer workload most frequently run on the RISC-V cores.
Two such critical Transformer functions to run on AX46MPV are the LayerNorm and Softmax kernels, which AX46MPV is able to achieve 30% to 70% improvements on variations of the two kernels over its predecessor, AX45MPV. For both functions, the AX46MPV achieves great performance improvement over AX45MPV without any hardware look-up table (LUT) or specialized hardware. Instead, this is strictly through mathematical algorithms that take advantage of the massive instruction level parallelism built-in for the AX46MPV vector core.
Equally important is the fact that the performance achievements are directly from LLVM compiler generated code across different tensor dimensions, not hand-written low-level codes. Since LLVM 16, the compiler has improved dramatically in auto-vectorization. The AX46MPV was developed to support LLVM compiler’s various optimizations such as software-pipelining, data interleaving, etc. to maximize the vectorization capability available in the underlying RISC-V vector instruction set. For example, the AX46MPV’s re-ordering buffer enables LLVM to maximize the use of RVV’s LMUL (register grouping) in many cases by re-using the registers in frequently used RVV compute sequences.
“It’s exciting to see AX46MPV excelling in customer’s production AI models, and smoothly into silicon fabrication,” said Alex Chen, Andes director of VLSI for the AX46MPV. “The cloud AI is our focus, and we will continue to leverage the AX46MP foundation to extend our leadership into all AI infrastructure silicon.”
The AX46MPV is the third generation of Andes’ RISC-V vector compute core, following the NX27V and AX45MPV, re-using much of the infrastructure that’s highly effective for Transformer based AI models. It starts with an RVA22 AX46MP and adds the vector extension (RVV) with a highly parallel Vector Processing Unit (VPU) which can execute up to five RVV operations in parallel, with full chaining & pipelining. In addition to the baseline RVV BF16 instructions, the AX46MPV also supports all RISC-V floating point instructions using BF16, ensuring seamless and automated LLVM code generation. To keep up with the memory demand, the AX46MPV has dramatically enhanced the High Bandwidth Vector Memory (HVM) subsystem with a crossbar design with up to 64 memory banks for up to 16 AX46MPVs to share. The AX46MPV incorporates the Andes Custom Extension™ (ACE) RISC-V ISA extension capability with automated compiler, COPILOT to encapsulate customers’ Matrix Engines, DMA engines, accelerator blocks, etc. into LLVM compiler friendly instructions. Finally, the AX46MPV supports the recently ratified RISC-V trace/debug standards for a complete solution with a rich third party debug/IDE ecosystem.
The AX46MPV is a highly configurable processor IP, as in all Andes cores. From single to 16 cores, user-configurable cache sizes / hierarchy, and the HVM crossbar; to width of the VPU (VLEN and DLEN), number of memory/MMIO ports, and most of the internal buffering, the AX46MPV is an expansive core that can fit into any cloud AI infrastructure SOC. In TSMC’s 3nm process, the AX46MPV achieves 1.5GHz worst case frequency in a typical configuration.
The AX46MPV begun shipment in Q1, 2025 to early licensees and production release in early October, 2025. For configuration, pricing, and other availability information please contact sales@andestech.com.
About Andes Technology
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, and consumer electronics applications spanning data centers, mobile devices. Over 17 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com .