Design & Reuse

TES offers CAN Flexible Data-Rate Controller IP Core for System-on-Chip (SoC) Designs

www.tes-dst.com, Jan. 09, 2026 – 

 

TES Electronic Solutions GmbH adds to its IP portfolio a new VHDL-based CAN Flexible Data-Rate (FD) controller IP core. The IP is designed for System-on-Chip (SoC) implementations and can be integrated into a wide range of applications and target technologies. It supports both ASIC and FPGA designs.

Key Benefits

- CAN FD Support: Compatible with the CAN FD protocol according to ISO 11898-1:2024 with data rates up to 8 Mbit/s.

- Configurable: The clock prescaler provides support for a wide frequency range. The digital interface can be configured according to the requirements of the application.

- RX Frame Filter: The optional RX frame filter allows filtering received data frames according to the identifier.  

- Verified According to ISO 16845-1: The IP has been digitally verified according to the ISO 16845-1 Road Vehicles – Controller Area Network Conformance Test Plan.

- First-Class Support: TES will make supporting your design effort a priority – whether it is integrating this IP into your design or implementing a complete ASIC.

For more information on this and other digital IP solutions, visit the TES IP products page.

Contact

For inquiries, please email sales@tes-dst.com

About TES

With over 20 years of experience in ASIC design and embedded graphics IP, TES is a one-stop partner for high-performance semiconductor solutions. Our IP portfolio includes highly customizable 2D, 2.5D, and 3D GPUsdisplay controllers, and a wide range of analog and digital IP blocks, ranging from SiGe RF to industrial ASIC solutions.

Headquartered near Stuttgart, Germany, TES Electronic Solutions GmbH serves a global customer base, with design operations in Stuttgart and graphics IP development in Hamburg. Learn more at www.tes-dst.com.