Enhancement Reduces Test Development Costs and Improves Time-To-MarketSAN JOSE, Calif. -- April 2, 2009
-- LogicVision, Inc. (Nasdaq: LGVN), a leading provider of semiconductor built-in-self-test (BIST) and diagnostic solutions, today announced a solution that will increase the ease and efficiency in reusing a growing number of cores containing embedded I/Os. LogicVision's field proven BIST solutions have driven more efficient core reuse in hundreds of designs as they enable cores to be handed-off with test completely integrated. With new cores increasingly containing chip I/O circuitry and pads, LogicVision's new embedded boundary scan solution allows needed I/O DFT structures to be added directly into these cores rather than later at the top level during full chip integration. This new capability results from LogicVision's ongoing goal to meet developing industry test needs and is indeed key to maintaining reduced test development costs and faster time-to-market when using these new types of cores.
Chip I/O cells are being placed directly into cores in order to be closer to the logic they service. This approach typically results in significant physical design benefits including reduced signal routing and improved timing. LogicVision's new embedded boundary scan capability allows boundary scan cells to be integrated alongside their associated I/O cells directly within the core. Boundary scan cells can be added to any core at any hierarchical level within a design. The solution automates both the integration of the boundary scan cells and verification of the resulting boundary scan segment within the core. This not only maintains and extends the physical design benefits of placing I/O cells directly into cores, but also enables a more efficient core re-use methodology as all design and DFT sign-off activity can take place fully at the core level.
The embedded boundary scan capability is also fully integrated with LogicVision's ETLogic(TM) logic BIST solution and further simplifies the integration of logic BIST into cores containing embedded I/Os.
"Hierarchical designs with embedded I/Os are quickly becoming the norm," said Stephen Pateras, Vice-President of Marketing at LogicVision. "Our new embedded boundary scan capability represents the remaining component within our family of solutions needed to provide a fully hierarchical DFT flow."
The embedded boundary scan capability is immediately available and is included within the existing Custom option to LogicVision's ETBoundary(TM) product. The ETBoundary Custom option also provides support for the seamless integration and verification of I/O pads containing integrated boundary scan cells.About LogicVision Inc.
LogicVision (Nasdaq: LGVN) provides a comprehensive set of proprietary built-in-self-test (BIST) technologies for achieving the highest quality silicon manufacturing test while reducing test costs for complex System-on-Chip devices. LogicVision's Dragonfly Test Platform(TM) enables integrated circuit designers to embed BIST functionality into a semiconductor design. This functionality is used during semiconductor production test and throughout the useful life of the chip. The complete Dragonfly Test Platform, including the ETCreate(TM), Silicon Insight(TM) and Yield Insight(TM) product families, improves profit margins by reducing device field returns and test costs, accelerating silicon bring-up times and shortening both time-to-market and time-to-yield. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com