English
Jasper Patent Speeds Debug During Verification
12th patent in expanding formal technology portfolio
Mountain View, Calif. – April 17, 2009 – Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design.”
The key benefit of this technology is that users performing functional verification on a circuit design can accelerate design analysis and debug, by removing the necessity for sequential tasks.
Jasper has now been granted 12 patents, with additional patents pending. Through continuous innovation and responsiveness to market requirements, Jasper delivers proven “Targeted ROI” to customers by solving their most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk. This philosophy is embodied in JasperGold®, the industry’s most powerful and effective deep formal verification solution; and ActiveDesign™ with Behavioral Indexing™ for accelerated legacy design and IP comprehension and reuse.
About Jasper Design Automation
Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
Mountain View, Calif. – April 17, 2009 – Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design.”
The key benefit of this technology is that users performing functional verification on a circuit design can accelerate design analysis and debug, by removing the necessity for sequential tasks.
Jasper has now been granted 12 patents, with additional patents pending. Through continuous innovation and responsiveness to market requirements, Jasper delivers proven “Targeted ROI” to customers by solving their most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk. This philosophy is embodied in JasperGold®, the industry’s most powerful and effective deep formal verification solution; and ActiveDesign™ with Behavioral Indexing™ for accelerated legacy design and IP comprehension and reuse.
About Jasper Design Automation
Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.
|
||||||
Related News
- GBT Receives Patent Grant Notification Covering its Integrated Circuits Reliability Verification Analysis and Auto-Correction Technology
- Cadence Verisium AI-Driven Verification Platform Accelerates Debug Productivity for Renesas
- Axiomise Unveils Intelligent Debug Solution for Formal Verification of RISC-V Cores
- SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio
- SmartDV Speeds Delivery of its New CXL Verification IP
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
|
E-mail This Article | 
|
|
Printer-Friendly Page |