Jasper Patent Speeds Debug During Verification

12th patent in expanding formal technology portfolio

Mountain View, Calif. – April 17, 2009 – Jasper Design Automation, provider of advanced formal technology solutions, today announced it has been awarded U.S. Patent No. 7,506,288 for “interactive analysis and debugging of a circuit design during functional verification of the circuit design.”

The key benefit of this technology is that users performing functional verification on a circuit design can accelerate design analysis and debug, by removing the necessity for sequential tasks.

Jasper has now been granted 12 patents, with additional patents pending. Through continuous innovation and responsiveness to market requirements, Jasper delivers proven “Targeted ROI” to customers by solving their most critical design challenges in ways that also speed time to market, reduce overhead, and mitigate risk. This philosophy is embodied in JasperGold®, the industry’s most powerful and effective deep formal verification solution; and ActiveDesign™ with Behavioral Indexing™ for accelerated legacy design and IP comprehension and reuse.

About Jasper Design Automation

Jasper delivers industry-leading EDA solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 100 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, India and Japan. Visit www.jasper-da.com for Targeted ROI: reducing risks; increasing design, verification and reuse productivity; and accelerating time to market.