Denali's High-Performance DDR2 Controller and VIP Products Deployed in Low-Power Baseband SoC for the 3G Mobile Market SUNNYVALE, Calif. -- April 22, 2009 --
Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that
Percello Ltd., a fabless semiconductor company developing digital baseband processor chips, has achieved first-pass silicon success with Denali's Databahn(TM) DDR memory controller IP and MMAV verification IP, successfully deployed in its low-power PRC6000 system-on-a-chip (SoC). Percello's PRC6000 is the first worldwide SoC solution dedicated for the emerging 3G UMTS and HSPA+ femtocell market. Denali's design and verification IP accelerated Percello's designers' ability to design DDR2 memory system, lower their integration risk, and speed their time-to-market for their new innovative cellular chip.
"Today's SoC design specifications necessitate high-quality IP and VIP and Denali's solutions and expertise unlike any other vendor. We were pleased with the unmatched performance and overall ease of integration of Denali's Databahn memory controllers into our chip design," said
Rafy Carmon, vice president of R&D at Percello Ltd. "We used Databahn controller and MMAV in our design to support our required DDR2 memory interface and TSMC's 65nm CMOS technology. During the design and verification phases, we found that Denali's IP and VIP were easy-to-use and to integrate which facilitated our very fast design cycle."
Percello's PRC6000 chip is a highly integrated device supporting all femtocell backhauling architectures and functions such as timing, security and others. PRC6000 is compliant to 3GPP Rel 7 baseline, supports 8 users simultaneously and is capable of delivering 21.6 Mbps downlink and 5.76 Mbps uplink.
DDR DRAM is a key component in many memory subsystems found in a variety of computing, networking and communications manufactured today. With DDR DRAMs achieving speed grades up to 1600 Mbps, high-performance DDR interfaces are a critical variable in overall system performance. To better address these challenges, designers need a high-quality, proven solution consisting of more than the digital DDR memory controllers.
"Today's high-performance SoCs require specialized DDR memory systems that must address several design criteria plus an aggressive time-to-market schedule," said
Marc Greenberg, director, technical marketing of IP products for Denali. "Our Databahn DDR controller and verification IP stellar reputation has really escalated in the industry allowing our customers to make an easier choice to address their application specific performance requirements. We are very content with Percello's first-pass silicon-success with their complex, high-performance SoC."
About MMAV Denali's MMAV product is the industry's de-facto standard solution for modeling and simulating memory during functional verification. MMAV has been used in thousands of designs to ensure correct and optimal behavior and timing between the system design and off-chip memory devices. MMAV utilizes a powerful and effective approach to modeling memory. MMAV 2008 is available immediately. Additional MMAV 2008 information and an evaluation can be requested at:
http://www.denali.com/mmav.
About Denali Software Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying
USB,
PCI Express,
NAND Flash and
DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in
Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at
www.denali.com.
