Magillem Design Services announces release of new Generation Register View
April 27, 2009 - Entering the market with a product targeting the traditional need of IC designers to manage the Registers, MAGILLEM is offering a brand new approach: Customers do not have to choose between an Excel based Register capture system, disconnected from their design, or an expensive, dedicated Register management tool, still not addressing the issues of collaborative work. Cost effective, and non-compromising, MRV by Magillem solves the dilemma.
One of the biggest challenges for any decent register centric solutions is to ensure the HW/SW synchronization. Synchronization means that different set of data evolve concurrently, representing different register facets or views of the IP targeting a specific use model: firmware data, hardware data, verification, documentation…
For most SOC designers worldwide, the problem is acute : views need to be merged or updated at some milestones in the flow. These views are owned by different groups of people having the rights and the knowledge for any modification of the dedicated facet. The Register centric design-environment must have the features to handle such synchronization, version handling, data inference... So far, all data were mixed up within the same bucket, jeopardizing data filled in by other owners. Same bucket doesn’t mean a unique file. Synchronization doesn't imply that all data generated in different targeted languages come from the same unique source. They come from multiple sources, multiple files which are now synchronized with MRV, ensuring that they comply with the same IP definition model and complement each others.
"The request for hierarchical views of the registers is also fulfilled thanks to MRV; the quality of its graphical interface improves the productivity drastically, for the first times register specification is synchronized with RTL and ESL design even during bottom up implementation!
Information on registers is captured once and for all, reducing the risk of errors. The comfort of interactive immediate handling of register bit fields and blocks of memory maps via the MRV GUI makes this new generation register management tool an undeniably compelling offering for the designers" says Cyril SPASEVSKI, CTO.
Unique features position MRV as the best-in-class tool:
- True synchronization with RTL or ESL platform : Visualize and edit the full project hierarchy
- True Hierarchical description: Single source based solutions can’t work for the next generation! Concurrent developments handle more than 500 different xml files containing memory map fragments. The relationship and the ordering, hierarchy defined in the project must be preserved.
- Complete Register and Bitfield editor, with move and resize, instead of a simple viewer
- Memory Map editor, Copy/Paste to move and replace memory blocks, Drag and drop registers inside the memory map
- Visual identification of overlaps for immediate debugging
Thanks to MGS, Magillem Generator Studio, flexible generators customization is performed thru native object oriented API, template-based engine or IP-XACT TGI. Last but not least, MRV Premium includes a leading-edge textual input language compliant with state-of-the-art Magillem, Eclipse and IP-XACT Technologies. MRV runs on Linux and Microsoft Windows XP/2000.
About MAGILLEM DESIGN SERVICES
Established by a team of seasoned engineers and a group of business angels in 2006, Magillem Design Services provides customers with tools and services that drastically reduce the global cost of complex design, help them preserve their independence from EDA vendors and their investment by relying on a worldwide adopted Xml format: IP-XACT by the SPIRIT consortium™ (soon to be IEEE 1685) to which MDS is a key contributor. Technology is worth over 8 million dollars.
Clients are semiconductors manufacturers (ASICs, ASSPs), system integrators and information technology companies engaged in the research, design, development, manufacturing and integration of advanced technology systems and products (using ASICs and FPGA).
The headquarters are in Paris, France with a subsidiary in the USA and sales office in Asia.
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