English
Achronix Taps Signali for 10/40/100Gbps Encryption IP in World's Fastest FPGAS
128-bit key size AES cores designed for use in high-performance applications such as GPON (Gigabit-capable Passive Optical Network)
SAN JOSE, Calif. -- May 06, 2009 -- Achronix Semiconductor, maker of the world's fastest field-programmable gate arrays (FPGAs), today announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster(TM) 1.5 GHz family.
These high-performance 128-bit key size AES cores, from Portland, Ore.-based Signali Corp., are targeted at 10 Gbps, 40 Gbps, and 100 Gbps applications. They demonstrate the speed of the Speedster FGPA fabric, as well as the balance between throughput performance and resource minimization achieved by the Signali Cores.
"High-end 10/40/100G applications demand the highest-capability encryption engines to ensure security," said Ali Burney, SerDes and IP marketing manager for Achronix Semiconductor Corporation. "Signali's implementation with Achronix high-performance FPGAs deliver peace of mind to system engineers while striking the right balance between resource allocation and performance."
The Achronix Speedster family, launched in September 2008 and offering three times the performance of conventional FPGAs, target traditional ASIC applications requiring high data throughput. Many of these also require increasingly sophisticated encryption algorithms to thwart hacking attempts from around the globe.
In order to achieve the performance and resource utilization targets, Signali implemented two configurations for the AES IP cores: a 16-bit core, aimed at 10 Gbps applications, features a pin-efficient 16-bit data path while a second, 128-bit data path core, targets 40 to 100 Gbps applications. Both cores use 128-bit keys and operate in CTR (counter) mode, designed for use in high-performance applications such as GPON (Gigabit-capable Passive Optical Network). The cores are provided in standard Verilog or VHDL RTL, together with simulation models, test benches and complete documentation.
"Information assurance is of major importance in many of the markets Achronix is serving, so our partnership is an ideal fit," said Mark Konopacky, responsible for business development for Signali. "Our expertise in design and implementation of computationally efficient, complex algorithms, coupled with our innovative development methodology, enabled Signali to quickly explore many different microarchitectures during our development work to find the one ideally suited for deployment on Achronix Speedster devices."
Signali uses its Quattro(TM) technology to transform high-level descriptions of data-intensive functions, such as AES, automatically into high-performance RTL. These tools allow very rapid algorithm and microarchitecture exploration at the design level, allowing the Signali's designers to quickly choose the best solution for specific implementation platforms. Quattro enabled Signali's engineers to maximize usage of the capabilities of the Achronix Speedster FPGA architecture.
About Signali
Privately held Signali Corp. provides custom IP cores targeted at complex mathematics, fixed-function DSP and cryptographic applications. Signali is a commercial spin-out from Galois Inc., founded in 1999 to use functional programming and formal methods to address challenges in information assurance and other government and industry problems. Find out more at http://www.signalicorp.com/
About Achronix
Achronix Semiconductor is a privately held fabless corporation based in San Jose, Calif. Achronix builds the world's fastest field programmable gate arrays (FPGAs) capable of up to 1.5 GHz peak performance. Achronix has sales offices and representatives in the United States, Europe, China, Japan, and Korea, and has research and design offices in Boston, Mass., Ithaca, N.Y., and Bangalore, India. Find out more at http://www.achronix.com.
SAN JOSE, Calif. -- May 06, 2009 -- Achronix Semiconductor, maker of the world's fastest field-programmable gate arrays (FPGAs), today announced the availability of new, high-performance Advanced Encryption Standard (AES) IP cores for its Speedster(TM) 1.5 GHz family.
These high-performance 128-bit key size AES cores, from Portland, Ore.-based Signali Corp., are targeted at 10 Gbps, 40 Gbps, and 100 Gbps applications. They demonstrate the speed of the Speedster FGPA fabric, as well as the balance between throughput performance and resource minimization achieved by the Signali Cores.
"High-end 10/40/100G applications demand the highest-capability encryption engines to ensure security," said Ali Burney, SerDes and IP marketing manager for Achronix Semiconductor Corporation. "Signali's implementation with Achronix high-performance FPGAs deliver peace of mind to system engineers while striking the right balance between resource allocation and performance."
The Achronix Speedster family, launched in September 2008 and offering three times the performance of conventional FPGAs, target traditional ASIC applications requiring high data throughput. Many of these also require increasingly sophisticated encryption algorithms to thwart hacking attempts from around the globe.
In order to achieve the performance and resource utilization targets, Signali implemented two configurations for the AES IP cores: a 16-bit core, aimed at 10 Gbps applications, features a pin-efficient 16-bit data path while a second, 128-bit data path core, targets 40 to 100 Gbps applications. Both cores use 128-bit keys and operate in CTR (counter) mode, designed for use in high-performance applications such as GPON (Gigabit-capable Passive Optical Network). The cores are provided in standard Verilog or VHDL RTL, together with simulation models, test benches and complete documentation.
"Information assurance is of major importance in many of the markets Achronix is serving, so our partnership is an ideal fit," said Mark Konopacky, responsible for business development for Signali. "Our expertise in design and implementation of computationally efficient, complex algorithms, coupled with our innovative development methodology, enabled Signali to quickly explore many different microarchitectures during our development work to find the one ideally suited for deployment on Achronix Speedster devices."
Signali uses its Quattro(TM) technology to transform high-level descriptions of data-intensive functions, such as AES, automatically into high-performance RTL. These tools allow very rapid algorithm and microarchitecture exploration at the design level, allowing the Signali's designers to quickly choose the best solution for specific implementation platforms. Quattro enabled Signali's engineers to maximize usage of the capabilities of the Achronix Speedster FPGA architecture.
About Signali
Privately held Signali Corp. provides custom IP cores targeted at complex mathematics, fixed-function DSP and cryptographic applications. Signali is a commercial spin-out from Galois Inc., founded in 1999 to use functional programming and formal methods to address challenges in information assurance and other government and industry problems. Find out more at http://www.signalicorp.com/
About Achronix
Achronix Semiconductor is a privately held fabless corporation based in San Jose, Calif. Achronix builds the world's fastest field programmable gate arrays (FPGAs) capable of up to 1.5 GHz peak performance. Achronix has sales offices and representatives in the United States, Europe, China, Japan, and Korea, and has research and design offices in Boston, Mass., Ithaca, N.Y., and Bangalore, India. Find out more at http://www.achronix.com.
|
||||||
Related News
- GL Communications Inc. selects Achronix Speedster22i FPGAs for 10/40/100G PacketExpert
- Synopsys Powers World's Fastest UCIe-Based Multi-Die Designs with New IP Operating at 40 Gbps
- Achronix FPGAs Add Support for Bluespec's Linux-capable RISC-V Soft Processors to Enable Scalable Processing
- PLDA Announces Industry's First Controller for FPGA supporting PCIe 4.0 v0.9, Allowing immediate PCIe 4.0 implementation into FPGAs
- Altera FPGAs Enable Big Data Storage Security with Advanced Encryption Standard Rates of an Unprecedented 100-Gbps, Full Duplex
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
|
E-mail This Article | 
|
|
Printer-Friendly Page |