English
Tokyo Electron Device Announces ASIC/LSI Prototyping Board Released Featuring DDR3 SDRAM and LV-DDR2 SDRAM
A Complete Development Platform to Interface with Next-generation Memories Using Xilinx Virtex(R)-5
Yokohama, Japan -- May 19, 2009 - Tokyo Electron Device Limited (TED) has today announced the release of Virtex-5 DDR3/LV-DDR2 SDRAM evaluation platform featuring next-generation high-speed DDR3 SDRAM memory and new LV-DDR2 SDRAM from Elpida Memory.
The inrevium* TB-5V-LX110-DDR3 is ideally suited for ASIC/LSI prototyping that can be used to test DDR3 SDRAM with a maximum speed of 1,066Mbps and LV-DDR2 SDRAM with a maximum speed of 667Mbps. This is the first FPGA evaluation platform to incorporate a DDR3 SODIMM (small outline dual in-line memory module) socket and is supplied with 1GByte DDR3 memory module. It can support DDR3 memory modules up to 4GByte.
The shift from DDR2 SDRAM to DDR3 SDRAM is already underway in products such as high-end PCs and servers. It is anticipated that use of DDR3 SDRAM will become increasingly widespread in products such as high-end digital consumer electronics and high-speed image processing devices. LV-DDR2 SDRAM is a low-power version of DDR2 SDRAM that can meet the demand from digital consumer electronics for lower power consumption and space saving with an operating power supply voltage of only 1.5V and a 32-bit interface that allows configurations in which two conventional 16-bit DDR2 SDRAMs are replaced with a single device.
DFI 2.0 (DDR PHY Interface) compatible DDR3 SDRAM PHY design for the Virtex-5 and DFI 1.0 compatible LV-DDR2 SDRAM PHY design for the Virtex-5 come with this platform can be realized to reduce total ASIC/ LSI development time by a seamless transition from FPGA to ASIC or LSI.
The inrevium TB-5V-LX110-DDR3 provides a flexible evaluation environment with a range of option boards such as DVI, ADC and DAC, Gigabit Ethernet, and LVDS and also the ability to connect to other large-scale FPGA evaluation platforms.
TB-5V-LX110-DDR3 features:
The inrevium TB-5V-LX110-DDR3 is available from June 2009 through distributors in the world wide. For pricing information, contact at psd-sales@teldevice.co.jp or TED's distributors.
For more product information, visit at
http://www.inrevium.jp/eng/x-fpga-board/tb-5v-lx110-ddr3.html
About Tokyo Electron Device
Tokyo Electron Device (TED) is a technical trading firm with a "trading business" function that provides semiconductor products and business solutions as well as a "development business" function that performs commissioned designing and the development of own-brand products.
URL: http://www.teldevice.co.jp/eng/
About inrevium
Leveraging on rich design and development experiences accumulated at its design development center that was established in 1985, Tokyo Electron Device is focusing on development businesses through its "inrevium" brand to provide design services (commissioned designing services) based on customer requirements as well as self- developed products that anticipate future market needs. Currently, TED provides over 60 types of products and will continue to engage in the high value-added development businesses.
URL: http://www.inrevium.jp/eng/
Yokohama, Japan -- May 19, 2009 - Tokyo Electron Device Limited (TED) has today announced the release of Virtex-5 DDR3/LV-DDR2 SDRAM evaluation platform featuring next-generation high-speed DDR3 SDRAM memory and new LV-DDR2 SDRAM from Elpida Memory.
The inrevium* TB-5V-LX110-DDR3 is ideally suited for ASIC/LSI prototyping that can be used to test DDR3 SDRAM with a maximum speed of 1,066Mbps and LV-DDR2 SDRAM with a maximum speed of 667Mbps. This is the first FPGA evaluation platform to incorporate a DDR3 SODIMM (small outline dual in-line memory module) socket and is supplied with 1GByte DDR3 memory module. It can support DDR3 memory modules up to 4GByte.
The shift from DDR2 SDRAM to DDR3 SDRAM is already underway in products such as high-end PCs and servers. It is anticipated that use of DDR3 SDRAM will become increasingly widespread in products such as high-end digital consumer electronics and high-speed image processing devices. LV-DDR2 SDRAM is a low-power version of DDR2 SDRAM that can meet the demand from digital consumer electronics for lower power consumption and space saving with an operating power supply voltage of only 1.5V and a 32-bit interface that allows configurations in which two conventional 16-bit DDR2 SDRAMs are replaced with a single device.
DFI 2.0 (DDR PHY Interface) compatible DDR3 SDRAM PHY design for the Virtex-5 and DFI 1.0 compatible LV-DDR2 SDRAM PHY design for the Virtex-5 come with this platform can be realized to reduce total ASIC/ LSI development time by a seamless transition from FPGA to ASIC or LSI.
The inrevium TB-5V-LX110-DDR3 provides a flexible evaluation environment with a range of option boards such as DVI, ADC and DAC, Gigabit Ethernet, and LVDS and also the ability to connect to other large-scale FPGA evaluation platforms.
TB-5V-LX110-DDR3 features:
- FPGA: Xilinx XC5VLX110-3FFG1760C
* XC5VLX330-2FFG1760C also available - PROM: Xilinx XCF128XFTG64C
- Memory: Elpida Memory DDR3 SDRAM: Chip (x 16-bit, 2pcs)
- LV-DDR2 SDRAM: Chip (x 32-bit, 1pc, 1.5V interface)
- LV-DDR2 SDRAM：Chip (x 16-bit, 1pc, 1.5V interface)
- DDR3 SDRAM: SO-DIMM socket (x 64-bit)
* 1Gbyte DDR3 SO-DIMM memory module is included - Power supply: Linear Technology LTM4601EV#PBF, LTC3413EFE#PBF, etc
- Operating clock: 200MHz oscillator
- PLL-IC
- SAMTECH MMCX connector
- Type A connector for option boards: 2pcs
- Push-button switches, LEDs, DIP switches, General-purpose pin header
- Reference designs (Verilog HDL)
- DFI 2.0 compatible DDR3 SDRAM PHY reference design for Virtex-5
- Reference design incorporating a write leveling function with a validated maximum operating speed of 1066Mbps (available for purchase)
- Reference design with a validated maximum operating speed of 800Mbps
- DFI 1.0 compatible LV-DDR2 SDRAM PHY reference design for Virtex-5
- DVI frame buffer design using DDR3 chips
The inrevium TB-5V-LX110-DDR3 is available from June 2009 through distributors in the world wide. For pricing information, contact at psd-sales@teldevice.co.jp or TED's distributors.
For more product information, visit at
http://www.inrevium.jp/eng/x-fpga-board/tb-5v-lx110-ddr3.html
About Tokyo Electron Device
Tokyo Electron Device (TED) is a technical trading firm with a "trading business" function that provides semiconductor products and business solutions as well as a "development business" function that performs commissioned designing and the development of own-brand products.
URL: http://www.teldevice.co.jp/eng/
About inrevium
Leveraging on rich design and development experiences accumulated at its design development center that was established in 1985, Tokyo Electron Device is focusing on development businesses through its "inrevium" brand to provide design services (commissioned designing services) based on customer requirements as well as self- developed products that anticipate future market needs. Currently, TED provides over 60 types of products and will continue to engage in the high value-added development businesses.
URL: http://www.inrevium.jp/eng/
|
||||||
Related News
- Tokyo Electron Device Announces New TB-OP-FCRAM Evaluation Board Released for Low Power Consumption Memory FCRAM
- Tokyo Electron Device Announces New Virtex-5 FPGA LX330 Evaluation Platform For ASIC Prototyping
- Tokyo Electron Device Announces Spartan-6 PCI Express Grabber Board supporting CameraLink PoCL
- Tokyo Electron Device Announces Release of TB-6V-LX760-LSI LSI Development Test Platform with Virtex-6 FPGA
- Denali Software and Tokyo Electron Device Unveil New DFI Compatible DDR2 SDRAM PHY for Xilinx FPGA
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
|
E-mail This Article | 
|
|
Printer-Friendly Page |