CAST Releases New Cores and Models at DAC'99
June 21, 1999, Design Automation Conference, New Orleans, Louisiana- Electronic intellectual property provider CAST, Inc. today announced additions to its inventory of synthesizable cores and simulation models for conventional and System-on-Chip (SOC) design.
The new cores include:
* the C82380 32-Bit Direct Memory Access (DMA) Controller,
* the R80515 Reduced-Instruction Set (RISC) Microprocessor,
* a new set of Wireless Telecommunications cores, and
* the C16450S and C16450S, synchronous versions of common universal asynchronous receiver/transmitter (UART) communications functions.
The new simulation models are part of the just-released 5.0 version of CAST's Standard Component VHDL Library (SCVL), a broad package of models for popular functions and devices.
All the new products will be demonstrated at the company's Design Automation Conference exhibit booth (#749). Datasheets and additional information can also be found at www.cast-inc.com.
New Cores Satisfy Customer Requests
Two of the new cores arise from direct customer requests.
The C82380 32-Bit DMA controller core provides an integrated set of peripheral support functions for 80386-based systems. Tadiran Telecommunications Ltd. (www.tadirantele.com) and others have ordered it as a replacement for an original device that Intel discontinued, helping these customers leverage their existing design investments. One major systems manufacturer, for example, is using it to enable the continuing production of a multi-million dollar product line.
The R80515 RISC version of CAST's C8051 microprocessor core was ordered by Siemens and intended for reuse in ASIC and FPGA implementations. This 8-bit microcontroller core executes instructions 2.5 times faster than the popular C8051, and actually operates 7.6 MIPs faster than the original Intel device. These performance gains are achieved through the elimination of redundant
bus states and the parallel running of the fetch and execution phases.
New Cores Support Wireless Applications
A comprehensive group of Wireless Telecommunications cores joins CAST's existing digital signal processing (DSP) functions to further support SOC designs in this rapidly-growing application area. The Wireless group includes Forward Error Correction cores (e.g., Viterbi decoder, Reed-Solomon encoder and decoder, and block interleaver/deinterleaver) plus additional filtering and signal processing functions.
Synchronous Versions of Serial Communications Devices CAST has also added enhanced versions of two existing cores. The C16450 Universal Asynchronous Receiver/Transmitter (UART) and the C16550 UART with FIFOs have each been redesigned to be completely synchronous, resulting in the C16450S and C16550S additions to the line. This use of synchronous logic helps designers minimize the potential timing problems that sometimes occur in designs using asynchronous logic. The asynchronous versions will still be available for designers needing to retain 100% compatibility with the original chips.
Simulation Model Changes for SCVL 5.0
The new CAST simulation models come as additions and enhancements to the company's long-running Standard Component VHDL Library (SCVL) product. This library includes a broad set of popular logic functions and memory devices, and is typically used for board-level simulation to verify new ASIC or FPGA devices in a realistic system environment. Customers with active CAST maintenance plans will receive the new SCVL 5.0 release for free.
The number of models included within SCVL has increased from 5500 to over 7200. New additions have been made to every category of model, and one new category has been added: Synchronous Static RAMs (SSRAMS).
A major customer-requested improvement to this new SCVL 5.0 release is the elimination of hardware keys for PC-based simulators. CAST has also rewritten the entire library to make greater use of VITAL functions, significantly improving the overall simulation speed of the models.
The ROM, SDRAM, and FLASH memory models within SCVL now include a new usability feature, the ability to load memory information data from a file.
The SDRAM models can read initialization data from multiple files for greater flexibility, and they can also dump their contents to a file during execution.
About CAST, Inc
CAST offers IP and design data management products backed by consulting, training, and custom development services. The company is headquartered near New York City at:
11 Stonewall Court, Woodcliff Lake, NJ 07675
Phone: 201-391-8300 Fax: 201-391-8694
E-mail: info@cast-inc Web: www.cast-inc.com
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Hal Barbour, CAST, Inc., 201/391-8300, firstname.lastname@example.org
Newton Abdalla, CAST, Inc., 914/354-4945, email@example.com
Paul Lindemann, PDL Communications, 603/434-3534