Compact, ultra-low power ARC EM processors and ASIL-Ready ARC EM Safety Island IP feature excellent code density
Denali Turbo-charges Rambus; Compaq's 'in'
Denali Turbo-charges Rambus; Compaq's 'in'
By Michael Santarini, EE Times
May 17, 1999 (9:29 a.m. EST)
Memory-modeling software provider Denali Software Inc. (Palo Alto, Calif.) has released its Turbo Channel simulation model for Rambus and announced that Compaq Computer Corp. is among the first systems houses to license the technology. Compaq will use the model in the development of next-generation Alpha processors.
Denali sells Turbo Channel as an option to its RDRAM verification kit, which it announced in October. According to company president Sanjay Srivastava, the new technology, which will be sold as an option to the RDRAM verification kit, models the Rambus channel rather than an individual memory component and as such will speed systems simulation as much as 20 times.
Rambus DRAM is a memory subsystem that promises to transfer up to 1.6 billion bytes per second. The subsystem consists of the RAM, the RAM controller, and the bus that connects the RAM to the microprocessor and other devices in the computer that use it.
"RD RAM has a new packet-based protocol," said Srivastava. "We created the new technology so customers could take full advantage of Rambus' performance. Turbo Channel allows them to build Rambus applications that are faster, and it offers them better memory-system debugging capabilities."
According to Srivastava, the Turbo Channel model, written in C, implements techniques for performance optimization when the Rambus Channel being modeled has many components connected to the channel.
The Turbo Channel model costs $5,000. Denali's RDRAM Verification kit, with the Turbo Channel model and Denali's AutoTest automatic-test-vector generation program and debugging software, costs $80,00.
Denali models and tools run on Windows and Unix platforms. See www.denalisoft.com.
Phoenix Technologies Ltd. (San Jose) has introduced a 10/100 Fast Ethernet medium-access controller (MAC) soft core featuring the Virtual Component Interface (VCI), a standard bus interface defined by the VSI Alliance to ease the integration of IP components onto one chip.
The company said the MAC core is the first offering in a planned family of interconnect cores that will use the VCI standard. The core complies with IEEE 802.3 and 802.3 specs and supports 10- and 100-Mbit/second data transfer.
The core also supports both full- and half-duplex modes, offering the CSMA/CD protocol for half-duplex operation and flow control (IEEE 802.3) for full-duplex operation.
According to Phoenix, the basic functionality of the core is fully implemented in hardware, eliminating the requirement for software drivers.
Features that are described as extending beyond basic MAC functionality include station management for PHY control, RMON network-management support, address filtering, clock synchronization, data handling and virtual-LAN support.
The company said the core is silicon-proven and undergoing compliance testing at the University of New Hampshire's Ethernet Interoperability Lab. Visit www.phoenix.com.
Search Silicon IP
- Rambus and Denali Sign License Agreement; Denali Integrates Rambus' Memory Controller IP into Databahn
- Rambus Inc. Adopts Register Description Language and Licenses Denali's Blueprint Software for IP Development Process
- Rambus to Demonstrate the World's Fastest Memory Device at Intel Developer Forum; New XDR DRAMs from Toshiba and Samsung Provide 8x the Bandwidth of Today's Main Memory
- Tachyum Integrates IP From World's Leading Vendors for Tape-Out In 2022
- Rambus Announces Departure of Ron Black as Chief Executive Officer; Luc Seraphin Appointed Interim CEO
- GlobalFoundries and STMicroelectronics Finalize Agreement for New 300mm Semiconductor Manufacturing Facility in France
- Microchip Slashes Time to Innovation with Industry's Most Power-Efficient Mid-Range FPGA Industrial Edge Stack, More Core Library IP and Conversion Tools
- Consortium's Move Will Boost RISC-V Ecosystem, Thankfully
- Are Chiplets Enough to Save Moore's Law?
- Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe
- Nanusens announces that it can now create ASICs with embedded sensors
- Intel Foundry Services Ushers in a New Era
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- MediaTek Partners With NVIDIA to Provide Full-Scale Product Roadmap to the Automotive Industry
- Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling
|E-mail This Article||Printer-Friendly Page|