Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Avalon Announces the Issue of their First US Patent
The invention provides a skew (delay) detection and skew correction apparatus for a high-speed data communications system with multiple data lanes. In FPGAs, skew occurs between transmission lines upon transmission startup. The invention ensures that the skew between all lanes falls within a certain tolerance, enabling the FPGA to adhere to the SFI-5 standard. Most FPGAs will be deficient without the use of this product, so Avalon is extremely pleased to have this patent.
Skew is detected and corrected through an iterative process which employs an algorithm to systematically iterate through a number of skew injection parameters for each of the data lanes to identify offsetting skew amounts to be injected into the data lanes to re-align the data lanes and achieve transmission line alignment.
Founder and CTO Wally Haas says, "Avalon is committed to Intellectual Property protection. This patent is a key differentiator for Avalon and many 40G FPGA designs in the marketplace could infringe on our IP. With the granting of this first patent and another seven non-provisional United States patent applications filed, Avalon extends its leadership in the optical transport market."
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