June 12, 2009 -- Noesis Technologies announced today the immediate availability of its new version of a
fully configurable Interleaver-Deinterleaver IP core (ntINT_DEINT).
The ntINT_DEINT is a fully configurable interleaver-deinterleaver compliant to a variety of industry standards such as DVB, ATSC, IEEE 802.16 e.t.c.
Its main features are the following:
- Supports Rectangular Block or Convolutional (de) interleaving.
- Rectangular Block (de) interleaver configuration:
- Block size
- Number of rows
- Number of columns
- Rows and/or columns permutations
- Convolutional (de) interleaver configuration:
- Number of branches
- Configurable branch length
- Supports continuous block data flow
- Configurable number of bits per symbol.
- Handshaking logic for I/O data flow control.
- Fully synchronous design, using single clock.
License options and availability ntINT_DEINT is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.
About Noesis Technologies Noesis Technologies is a leading provider of Forward Error Correction IP core solutions. Noesis Technologies specializes in the design, development and marketing of high quality, cost effective communication IP cores and provides VLSI design services. Its field of expertise include Forward Error Correction, Cryptography and Networking technology. In these fields, a broad range of high quality IP cores are offered.
Noesis IP cores have been licensed worldwide and its impressive list of customers ranges from large companies to dynamic startups in diverse market sectors such telecommunications, networking, military, industrial control and lower-power portable.
For more information and detailed datasheets please email your request at
info@noesis-tech.com
