TSMC Reports Foundry's First 28 Nanometer Low Power Platform Technology with Fully Functional 64Mb SRAM
Additionally, the paper reports good 64Mb SRAM functional yield with a competitive cell size of 0.127 um², and a raw gate density as high as 3900 kGate/mm² in this 28nm dual/triple gate oxide SoC technology. Good SRAM Vcc_min, electrical fuse, and analog performance have also been achieved which proves the manufacturability of this technology.
This leading edge technology demonstrates TSMC’s commitment and ability to extend SiON/Poly as a cost-effective solution for low power and high performance. In the paper presented, low standby and low operating power transistors using SiON optimized with strain engineering and aggressive oxide thickness provide up to 25~40% speed improvement or 30~50% active power reduction over prior 45nm technology.
“This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology,” said Dr. Jack Sun, vice president R&D at TSMC. “We continue this quest to support the most advanced applications being designed by the innovators in the semiconductor industry,” he said.
In the previous announcement made in September 2008, TSMC plans to deliver its 28nm process in early 2010 as a full node technology offering options of power-efficient high performance and lower power technologies. TSMC is now on track to deliver 28nmtechnology platforms to its customers.
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