ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics Focus on Enhanced Power Savings and Interoperability with Latest VersionSUNNYVALE, Calif., June 23, 2009
-- Denali Software, Inc., as one of the DDR-PHY Interface (DFI) specification participating members, today announced the release of the official DFI specification version 2.1. The significant momentum and support for the DFI specification has led to over 3,880 user downloads of the specification. The DFI specification version 2.1 is now available on the DFI community website (www.ddr-phy.or
) and includes low-power features supporting DDR3 and the newly released LP-DDR2 memory technologies from JEDEC. Some of the significant features in the latest specification enables low-power PHY, frequency change and frequency ratio options. The collaborative technical working group includes members from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics, and will be represented in the DFI exhibit booth at Denali MemCon, June 22-24 in Santa Clara, CA (www.memcon.com
"As the industry continues to demand higher performance and an enriched user experience in consumer products, energy efficiency and overall system costs becomes paramount design considerations," said Simon Segars, EVP and general manager, Physical IP division at ARM. "As the leader in high performance, energy efficient processor IP we fully support the DFI standards for DDR design. DFI 2.1 aligns with our goal of delivering unparallel low power end-to-end solutions to the embedded design community."
"As SoC designs migrate from DDR2 to DDR3 technologies to take advantage of the performance benefits, there is a strong need to reduce the integration effort by using a standardized interface between the DDR3 controller and PHY," said Don Friedberg, director of Foundation IP Solutions at LSI Corporation. "The contributions from LSI and others on the DFI technical working group have resulted in a standardized interface that is both easy to integrate and provides access to critical memory technology features. We look forward to wide usage of this specification across the industry."
DDR3 support, introduced in DFI 2.0, benefits from all of the low power features added in the latest revision, making a more compelling solution for power sensitive designs. The new frequency ratio support, which allows the memory to operate at a data rate of up to 8X the memory controller clock frequency, is critical to supporting DDR3 memories operating at the upper end of the supported frequency range.
"The recent growth in the DDR IP marketplace has proven to be a fruitful environment for the development of the DFI interface specifications," said Navraj Nandra, director of product marketing at Synopsys, Inc. "Synopsys has begun to incorporate DFI 2.1 support into our broad portfolio of high-quality DesignWare DDR IP solutions beginning with our high-performance DDR3/2 PHYs supporting data rates up to 2133Mbps."
"The DFI2.1 specification is designed to allow users to future-proof their SoCs in the ever-advancing DDR2/3 and LP-DDR2 technology space," said Kamalesh N. Ruparel, vice president and general manager, ASIP Solutions, Virage Logic. "As the industry's trusted IP partner, Virage Logic is committed to providing technically differentiated, silicon proven IP solutions that are standards compliant. With this goal in mind, the Intelli(TM) DDR multi-protocol solution has been architected to be DFI 2.1 standard compliant while delivering high efficiency, increased performance and bandwidth, at the lowest power possible."
"We have seen significant customer pull for the features now delivered in the DFI 2.1 specification, namely support for the LP-DDR2 memory protocol and the new low-power features," states David Lin, vice president of Marketing for Denali. "Denali would like to thank our fellow DFI team members for their efforts and contributions to the continued development of this specification. The DFI ecosystem continues to grow and this release will surely enable new and speedier semiconductor support for LP-DDR2 memories."About the DFI Specification
The DDR-PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org
.About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying USB
, PCI Express
, NAND Flash
and DDR DRAM
subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com