SANTA CLARA, Calif. A company with plans to leverage DSP algorithm R&D conducted in Ireland into a leading position in the intellectual-property (IP) cores market presented a series of innovative DSP coprocessor cores at IP99.
Massana Inc. (Campbell Calif.) is now based in Silicon Valley but has its engineering base in Dublin, Ireland, where it began three years ago to provide design services. The company said it already has Alcatel, Analog Devices, Motorola, Nortel and Toshiba as clients or partners.
Massana is making its thrust into the IP-cores business with the Filu series of DSP coprocessor cores. Those are intended to use a small amount of silicon area to add significant DSP capability to a conventional microcontroller or microprocessor host.
The cores have also been crafted to be C-language-friendly, said Paul Costigan, president and chief executive officer of Massana. "Users can develop their application entirely in C and use an application programming interface to invoke Filu functions," Costigan said.
The cores are accessed through a C-function call from a host microcontroller or microprocessor. The cores' microcoded kernel includes FIR and IIR filters, FFTs, correlations, matrix operations and Taylor-series calculators. While the primary set of operations is hardwired, the use of RAM can extend the functionality after production.
Massana has parameterized the technology behind the cores with its MWare generator, which quickly produces cores of specific word lengths and register count. The cores are then supplied to licensees in the form of a synthesizable Verilog file, together with a C++ model to allow high-level simulation.
The company's conference paper demonstrated the use of the 7,000-gate Filu-50 in an automotive application. The small gate count translates to an area of just 0.35-mm2 in a 0.35-micron CMOS process and is about one-quarter the size of a conventional DSP core.
The Filu-50 is des cribed as a 16-bit DSP core achieving 50 Mips when run at a clock frequency of 100 MHz. Costigan described the Filu-50 as being competitive in performance with the TMS320C50 of Texas Instruments, the Oak DSP core from DSP Group and the 56116 from Motorola. Typical applications are listed as disk-drive servo control, ac/dc motor control, and engine management and engine-knock detection.
The Filu-200 is a 16-bit core but features a 20-bit internal architecture and dual multiplier accumulators. This takes the gate count up to 30,000, but allows the core to achieve 200 Mips if implemented in a 0.25-micron process.
Applications for the Filu-200 include soft modems and speech and audio processing.
Costigan's IP99 paper also included an implementation of the Filu-200 as coprocessor to a 32-bit RISC core in a G.Lite ADSL application.
Massana has implemented the Filu-50 in a Xilinx FPGA where it runs at 20 MHz and yields 10 Mips. The company is going to 0.35 micron dedicated silicon late in the second quarter. Similarly, the Filu-200 is scheduled to be manufactured by Taiwan Semiconductor Manufacturing Co. in 0.25-micron CMOS in a multiproject wafer run at about the same time.
Massana was spun out of a DSP research group at University College Dublin (UCD) in 1996. The company has assembled a team of about 20 engineers, many of whom are Irish nationals who have returned to Ireland from jobs in Europe. Costigan himself held engineering positions with Alcatel Telecom (Antwerp, Belgium) and Digital Equipment Corp. (Westboro, Mass.) before returning to carry out research at UCD.
Although Massana started in Dublin as a provider of VLSI design services, Costigan explained that the service offering was used to provide a revenue stream while the company readied an IP product that could be licensed to chip makers.
Massana is close to completing its next round of financing, said to be $5 million, which the company will use to fund its expansion over the next two years.
Following its initial Filu ser ies of low-cost DSP compute engines, Costigan said Massana intends to release a Fast Ethernet core for use in the physical layer and is developing a Gigabit Ethernet physical-layer technology.