IP99: Synopsys aims to make design reuse practical

IP99: Synopsys aims to make design reuse practical
By Richard Goering, EE Times
March 24, 1999 (2:34 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990324S0020

SANTA CLARA, Calif. — Taking steps to make design reuse more practical for its users, Synopsys Inc. (Mountain View, Calif.) released a broad suite of tools for intellectual-property (IP) creators and integrators at the IP99 Conference. Synopsys also announced the addition of complex IP blocks, including a PCI core, to the company's DesignWare library for free distribution to Synopsys Design Compiler users.

Three of the tools in Synopsys' announcement were expected, including CoreBuilder, used by IP creators to encapsulate design knowledge into a compiled object form; CoreConsultant, used by IP integrators to "unpack" and synthesize the compiled IP; and CoreMill, used by IP creators for timing characterization of hard cores.

Added to this list is VeraCore, which captures and packages reusable test benches that can be shipped with a core independently of language, platform or simulator. Synopsys also announced a Web-based IP Catalyst Catalog, which provides ratings of IP based on the More assessment program announced in December by Synopsys.

Those announcements comprise strategic moves that Synopsys believes will help it fend off synthesis competition from other vendors, particularly Cadence Design Systems Inc. The IP created with CoreBuilder will be difficult to use with any synthesis tool other than Design Compiler, and users of that synthesis product will have free access to increasingly complex cores. The third-party market for PCI cores, and other standard bus interfaces, could be threatened as a result.

"We've tried to develop tools and methodologies that enhance the value of IP so that reuse is greatly facilitated," said Aart de Geus, chief executive officer of Synopsys. He said Synopsys' offerings provide, for the first time, a "semiautomatic formalism" for IP reuse.

De Geus said the new offerings address five areas: the need to create, pack, distribute, unpack and inte grate IP. In the creation area is VeraCore, which allows IP developers to create test benches in Synopsys' Vera language. "You need to capture information on how to test IP, so we have a testbench wrapper and unwrapper," said de Geus.

VeraCore includes three components: a stimulus generator, a results checker and a coverage analyzer. All are delivered along with the IP to the integrator, who does not need to purchase a Vera license to run and check the testbench.

CoreBuilder, which de Geus described as "guided knowledge capture," is intended to help users "pack" IP. It captures IP into encrypted "CoreKit" files for delivery to the end user. With CoreBuilder, developers can capture design intent without having to write synthesis scripts.

What the IP user sees, however, is CoreConsultant, which "unpacks" the CoreKits. "You can think of CoreConsultant as like the Adobe Acrobat reader," said Raul Camposano, chief technical officer at Synopsys. "We'll provide it for free, and it allows whoever uses Co reBuilder to deploy IP very quickly."

For the IP integrator, Camposano said, CoreConsultant is like having "three experts in a box" — the original core designer, an applications engineer, and a synthesis expert. CoreConsultant guides the user through configuration, synthesis and results analysis, so that users only execute steps that have required data.

To help the packing process for hard IP, Synopsys has introduced CoreMill, a characterization tool based on the PathMill timing engine. It lets IP providers generate timing models in a variety of formats, such as Stamp and Verilog, and to package and send those models to the end user.

To distribute IP, Synopsys is expanding its DesignWare library, which has been shipped to over 8,000 users. Until now, it's consisted of lower-level building blocks. The first complex IP to join the library includes the DW16550 UART, the DW8051 microcontroller, and the DWPCI 64-bit, 66-MHz PCI 2.2 compliant bus interface. Synopsys intends to add other standard bus interfaces.

"We will enable every designer to use these parts without having to go through a complex effort to acquire them," said Camposano. "There are no contracts, per-use fees or royalties."

Asked about the possible impact on third-party providers of such cores, de Geus said it's all part of a "natural evolution" in which increasingly complex blocks are becoming commodity items. "There is no differentiation in PCI cores," he said.

One complex core that will be joining the DesignWare library is the NGIO core being co-developed by Synopsys and Intel Corp. At Synopsys' IP99 announcement, Mitch Shults, Intel's director of NGIO initiative marketing, said that Intel will use VeraCore, CoreBuilder and CoreConsultant in the creation of the core.

John Chilton, vice president of Synopsys' design reuse group, said the new tools won't lock users into a Synopsys flow. With TCL scripting capabilities, he said, any verification tool can be used by creators or integrators. But the same is not true of synthesis. "It's possible to get the IP onto another synthesis tool, but it will be very clumsy," he said.

At present, Synopsys holds the vast majority of the ASIC synthesis market. But that's not necessarily the case with FPGA synthesis, where companies such as Exemplar and Synplicity divide the pie. Chilton said that Synopsys is not currently targeting FPGAs with its IP tool offerings, but expects to do so within the next six months.