Reference Flow Aims to Create a Healthy Eco-System of “Ready to Integrate” IPs Through Atrenta SpyLinks™ ProgramSAN JOSE, Calif.-- July 07, 2009 --
Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced a collaboration with Sonics, Inc., and Denali Software, Inc., to build a reference flow based on Atrenta’s 1Team®-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor intellectual property (IP) that is qualified and ready to use in automated system-on-chip (SoC) assembly.
The collaboration, launched under Atrenta’s SpyLinks™ partner program, enables IP suppliers to ensure seamless integration of their IP portfolio into the 1Team-Genesis automated chip assembly and feasibility analysis solution. The result of this collaboration is a reference flow that defines the interfaces to the supplier’s IP generators, pre-qualifies their IP-XACT™ models and ensures that the generated RTL is “SpyGlass® clean.”
Atrenta plans to expand the collaboration to a broad set of IP suppliers to help create a healthy eco-system of ready-to-integrate IP. This program is open to all IP suppliers, both commercial and captive, including providers of bus fabrics, processors, DSPs, interface IPs, memories, controllers, and any other IP relevant to SoC design.
“The efficiency and time-to-market benefits of platform-based design and rapid chip assembly are significant,” said Piyush Sancheti, senior director of business development at Atrenta. “With 1Team-Genesis, we have built a best-in-class chip assembly and feasibility analysis solution. This collaboration with our SpyLinks IP partners is an important step toward making SoC design truly 'plug-and-play' for our customers, thus preventing chip integration woes.”
“Sonics’ value is allowing our customers to add any IP, from any source at any time,” said Jack Browne, senior vice president of marketing and sales at Sonics, Inc. “Our on-chip-network IP must be highly configurable as customers integrate 50 or more IP blocks from multiple sources into a single SoC. Sonics is pleased to be working with Atrenta’s 1Team-Genesis to provide an SoC assembly platform that makes it easy for the SoC developer to configure the on-chip-network for connectivity of all the components in the system. This collaboration will provide a significant productivity boost for chip architects.”
“Memory access speed is a critical design consideration for most chips today. Our Databahn™ DRAM controller is widely used in the industry for an optimal interface between the IC and DRAM devices,” said Marc Greenberg, director, technical marketing at Denali Software, Inc. “Databahn is fully configurable for performance, power, and port arbitration. This collaboration with Atrenta makes it possible for SoC architects to explore feasibility of their architecture and then dial-in the parameters and generate an appropriate Databahn configuration. This is powerful stuff.”
Atrenta, Sonics, and Denali will showcase the results of their collaboration in a joint demonstration of an automated chip assembly flow in Atrenta’s booth at the 46th Design Automation Conference in San Francisco. For details and signup, please visit: http://www.atrenta.com/dac2009/sessions.htmlAbout Atrenta
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com
. Atrenta, Right from the Start!