IP99: Programmable role explored for system-chip ICs

IP99: Programmable role explored for system-chip ICs
By Peter Clarke, EE Times
March 23, 1999 (3:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990323S0018

SANTA CLARA, Calif. — Dataquest Inc. will begin to track market statistics for application specific programmable products (ASPPs), chips that combine programmable logic with diffused cores.

Dataquest's decision, announced at a panel session on Monday (March 22) prior to the opening of IP99, lends weight to such combination chips already launched by Lucent Technologies. QuickLogic Corp., sponsor of the "Programmability in the System-on-Chip World" session, will cast itself as an ASPP vendor with a range of QuickESP (for embedded standard product) devices, said vice president and founder John Birkner. QuickLogic could create QuickESPs based on patches of SRAM and numerous standardized interfaces, including PCI, Sonet, Rambus, USB and IEEE 1394, Birkner said.

Bryan Lewis, senior analyst at Dataquest (San Jose, Calif.), declared himself an advocate of ASPPs but cast some doubt on how quickly the market for the products would grow. Although the re is a strong need for ASPPs, Lewis said a complex set of issues surrounding both FPGA and ASIC technologies could push out the market's development another five to 10 years.

Lewis opened the panel by postulating three primary methods by which programmability would be used: as a small patch of programmable logic in an ASIC; as an FPGA with one or two broadly useful functions embedded in the device; or as a continuation of the status quo with ever-larger FPGAs being used to contain "soft" IP that could be used to build systems.

A broad set of issues has inhibited the ASPP approach to date and will determine whether monolithic combinations of programmable-logic ASIC technology can find a niche in the future, Lewis said.

ASPPs have made a slow start because the inefficiency of laying down logic in a PLD or FPGA hasn't been offset as yet by the devices' time-to-market or design-flexibility advantages. Second, the different design flows used by different communities of engineers have also inhibited t he market, he said. But the landscape has changed with the scaling of process technology, he said. "You have to ask yourself, is it cheap enough to do ASPP at this time? We believe it will be at that 0.13-micron process geometry.

"The PLD vendors will have to license their technology and therefore could be holding the wild card," he added.

Bob Payne, vice president of strategic technology at VLSI Technology Inc. (San Jose, Calif.), argued in favor of programmability from the position of an ASIC vendor.

Payne said that an SRAM-based FPGA architecture can be 100 to 200 times less efficient in its use of area than a cell-based design, and that a flash-based architecture can be 25 to 50 times less area efficient. Payne pointed out that a gap is opening up in the industry between what is manufacturable and what is designable.

Programmable logic could be a useful way to make use of the additional die area that's becoming available, Payne said. "This is a way to bring system-on-chip to the masses," he said. "System-on-chip in cell-based ASIC is restricted because of the high mask costs and high manufacturing volume requirements."

A less sanguine view was expressed by Mike Dini, president of Dini Group (La Jolla, Calif.), a design services company. "I am not a fan of the models presented," he said. "System-on-chip has not worked well in ASIC. Much of it is hype." As the head of a company that designs FPGAs, ASICs and boards containing these devices, Dini spoke in favor of the continued specialization of devices. Dini said he believed his engineers will continue to design larger FPGAs, more complex ASICs and separate memories.