Faraday Launches Its Low-leakage Memory with Up to 90% Leakage-reduction

Hsinchu, Taiwan -- July 14, 2009 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of low leakage memory at UMC 90nm process, which provides up to 90% leakage reduction with no area penalty. Faraday's low leakage memory has been silicon proven via complete function verifications, targeting fabless design houses, foundries, system vendors and IDMs.

As the development of advanced node, the percentage of memory on the chip is increasing, which distinguishes its potential impact in terms of both area and power consumption. Faraday's low leakage memory brings 25% power leakage reduction in stand-by mode; with two embedded HVT power gating MOS separately for Cell array and peripheral in the power configuration, the power leakage decreases up to 50% and 99% respectively in the retention mode and sleep mode. Exceeding expectations, the power MOS is distributed over and stuffed up the space in the memory core; the newly-unveiled memory performs the effective leakage reduction with no area penalty.

"We are very glad to offer our customers the performative low-leakage and area-saving memory," said Eliot Chen, Associate Vice President of IP Development at Faraday. "Contributed by the long-term technology development in low power field and accumulated abundant experiences interacting with customers, the newly-launched memory is designed not only to meet the arising demand from customers, but also to be more user-friendly to shorten customers' learning curve and reduce their implementation risk. Following with its availability at 90nm, the one at 55nm is expected to happen soon in Q4, 2009," he added.

Faraday's low leakage memory with two extra modes of retention and sleep is easy to operate with a simple truth table; users need to consider only 3 timing constrains (RET/SLP hold time, time for output being forced to zero, and time for power recovery) when switching the mode. Besides the port model, ring model with user-selectable ring layer and ringless model are available for customers' product differentiation. Furthermore, current spike prevention at wakeup is also considered to make sure of a stable power source quality. These have been all highly recognized by customers as thoughtful designs beyond their expectation.

"While migrating to the deep submicron process, memory design is becoming more complicated due to the device variability and increased array redundancy," said Steve Wang, Chief Strategy Officer at Faraday. "The market trend and customer demand for low leakage increases; it becomes an upmost requirement in specification. Faraday is optimistic in the market of low leakage memory and confident that our low leakage memory will bring our customers with more market successes and benefits," he added.

About Faraday Technology Corporation

Faraday Technology Corporation is a leading fables ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2008 revenue of US$ 149 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com.