English
nSys Demonstrates Verification IP for PCIe 3.0 at the PCI-SIG DevCon 2009
Newark -- July 15, 2009 -- nSys Design Systems will demonstrate Verification IP for PCIe® 3.0, which is currently at preliminary revision 0.5, at the PCI-SIG® DevCon 2009, to be held in Santa Clara, CA on July 15-16, 2009.
“In our endeavor to take PCI to the next generation, we have consistently relied upon PCI-SIG member companies including nSys as part of the PCIe ecosystem,” said Al Yanes, chairman and president, PCI-SIG. “nSys has been actively sponsoring PCI-SIG developers conferences around the world for more than five years now and we appreciate their willingness to share their experiences and expertise by presenting papers that benefit other members.”
“nSys has a comprehensive Verification IP for PCIe 2.0/ 1.0, in native Verilog and SystemVerilog,” said Atul Bhatia, CEO, nSys Design Systems. “As PCIe 3.0 is still evolving, it is our endeavor as an observer of the protocol working group, to make available the interim solutions for Verification IP to industry leaders.”
About nSys
nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs for its customers developing ASIC, FPGA or IP. The nVS family has proven Verification IPs in SystemVerilog and Verilog for standard interfaces/protocols such as PCI Express, SATA, SAS, AXI, AHB, APB, USB 2.0, SuperSpeed USB 3.0, DDR2, DDR3, Ethernet etc. For more information, please visit nSys online at www.nsysinc.com
About PCI-SIG
The PCI Special Interest Group (PCI-SIG) actively promotes PCI technology through a series of events. Members can test products at compliance workshops, receive PCI training at technical update seminars, participate in industry education and aid in promoting PCI technology at select tradeshows. For further information visit www.pcisig.com
“In our endeavor to take PCI to the next generation, we have consistently relied upon PCI-SIG member companies including nSys as part of the PCIe ecosystem,” said Al Yanes, chairman and president, PCI-SIG. “nSys has been actively sponsoring PCI-SIG developers conferences around the world for more than five years now and we appreciate their willingness to share their experiences and expertise by presenting papers that benefit other members.”
“nSys has a comprehensive Verification IP for PCIe 2.0/ 1.0, in native Verilog and SystemVerilog,” said Atul Bhatia, CEO, nSys Design Systems. “As PCIe 3.0 is still evolving, it is our endeavor as an observer of the protocol working group, to make available the interim solutions for Verification IP to industry leaders.”
About nSys
nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs for its customers developing ASIC, FPGA or IP. The nVS family has proven Verification IPs in SystemVerilog and Verilog for standard interfaces/protocols such as PCI Express, SATA, SAS, AXI, AHB, APB, USB 2.0, SuperSpeed USB 3.0, DDR2, DDR3, Ethernet etc. For more information, please visit nSys online at www.nsysinc.com
About PCI-SIG
The PCI Special Interest Group (PCI-SIG) actively promotes PCI technology through a series of events. Members can test products at compliance workshops, receive PCI training at technical update seminars, participate in industry education and aid in promoting PCI technology at select tradeshows. For further information visit www.pcisig.com
|
||||||
Related News
- Mobiveil's GPEX PCI Express 3.0 IP Passes PCI-SIG PCIe 3.0 Compliance Testing
- PLDA's XpressRICH3-AXI PCI Express 3.0 IP with AMBA AXI Support Passes PCI-SIG PCIe 3.0 Compliance Testing
- PLDA's XpressRICH3 PCI Express 3.0 IP Passes PCI-SIG PCIe 3.0 Compliance Testing
- Northwest Logic's PCI Express 3.0 Solution passes PCI-SIG PCIe 3.0 Compliance Testing at First Official PCIe 3.0 Compliance Workshop
- Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
|
E-mail This Article | 
|
|
Printer-Friendly Page |