IP99: Synopsys readies IP-reuse tools

IP99: Synopsys readies IP-reuse tools
By Richard Goering, EE Times
March 19, 1999 (4:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990319S0006

MOUNTAIN VIEW, Calif. — A new suite of tools that could greatly simplify the creation and use of soft intellectual-property cores will be announced at the IP99 Conference by Synopsys Inc. next week, EE Times has learned. Synopsys is also expected to release a tool that should assist with portability of hard IP.

A new E-Mail Synopsys Users Group (ESNUG) posting contains detailed descriptions of Synopsys' CoreBuilder and CoreConsultant, which respectively target creators and integrators of soft IP. The tools will join CoreMill, a tool for static timing verification and characterization of hard IP that came to light at a presentation in Japan last year.

A Synopsys spokesman said the three tools are "pieces of an overall plan" that will unfold at IP99, but he declined to provide details. John Chilton, vice president and general manager of Synopsys' design reuse group, said t hat the ESNUG posting is "generally accurate" but that it does not cover all of CoreBuilder's and CoreConsultant's capabilities.

In the ESNUG posting, an unidentified user described CoreBuilder as a graphical tool that captures IP into "CoreKit" files. The files are encrypted into a proprietary ".kb" format and delivered to the IP user. That person uses CoreConsultant to help automate synthesis runs with Synopsys' Design Compiler, thus producing a gate-level net-list from the .kb files.

"It's good stuff," the user wrote. "I think IP buyers will look forward to the end of grubbing around in someone else's RTL [register-transfer level code] and scripts and trying to figure out where they've hidden that last parameter."

The tools should interest all types of IP providers, said analyst Rita Glover, president of EDA Today (Phoenix). "They will help make the market more vibrant," she said. "We haven't had good IP packaging technology."

Gary Smith, principal EDA analyst at Dataquest Inc. (San Jose, Calif.), said the new tools appear to be part of a "disjointed" effort between Synopsys and Mentor Graphics Corp. to come up with offerings that support the principles in the Reuse Methodology Manual (RMM) they co-authored. "Overall, what these guys are trying to do is really neat, but the coordination is a little spotty," he said.

Candace Worley, marketing manager for Mentor's Inventra IP unit, said that Mentor does not normally partner on tool development and that it was not involved with the creation of CoreBuilder or CoreConsultant. She said the tools sound "useful" because they appear to make IP more readily usable with Design Compiler.

Smith also said the new tools appear related to the More IP rating system that Synopsys announced late last year. That system measures compliance with the RMM.

ESNUG moderator John Cooley said CoreConsultant looks like a product that will make i t "fairly painless" to integrate IP cores into chip designs. But Cooley said he's hearing concerns that the new tools and the proprietary .kb format will lock users into a Synopsys tool flow.

ESNUG reader Dave Brier said his "first reaction is that it is yet another proprietary encryption technique. An IP developer at Texas Instruments Inc.'s ASIC division, Brier expressed concerns that the gate-level designs that come out of CoreConsultant could still be reverse-engineered, and he said there's no indication that the Synopsys tools produce encrypted simulation models.

The tools were developed after Synopsys' first failed attempt to deliver a configurable PCI core. "For almost two years, we have successfully been using an early version of this technology to deliver our completely revamped DesignWare PCI core, to excellent reviews," said Chilton.

The unidentified ESNUG user described CoreBuilder as supporting both graphical entry and a command-line interface. By incorporating Design Compiler pragma s into the design, the user noted, IP developers can put configuration options into their RTL code that will appear as dialog boxes in CoreConsultant.

The user wrote that CoreBuilder helped capture design intent, "identifying the clocks, identifying any asynchronous reset signals — all the usual stuff that you'd have to do writing the dc synthesis scripts, except I didn't have to write a single line of script anywhere." The final stage of CoreBuilder involves determining what goes into the design kit prepared for the IP integrator.

"CoreConsultant runs like an automated unzip process, unpacking the design and then dropping it into a checklist of stages that the IP buyer has to go through to be able to synthesize the IP," the user wrote. The checklist walks the user through such stages as specifying target technology, configuring parameters and setting up the synthesis strategy. Selections can be made from pull-down menus.

Once the configuration is specified, CoreConsultant generates RTL tes t benches and documentation. In the last part of the checklist, the user tells CoreConsultant to run synthesis and to analyze the results. The last items "are mostly just fancy, multichoice GUIs driving Design Compiler," the user wrote.

CoreMill differs from the other tools because it focuses on hard IP. The product is from Synopsys' Epic division and is built on top of the PathMill static timing analyzer. One target of the tool is companies that wish to characterize the timing of hard IP for in-house reuse.

CoreMill originally had been scheduled for limited availability last September.