MIPI I3C Controllers - Dual Role Master (70016); APB I3C Slave (70002), Generic I3C Slave
OVM World Collaborates on Accellera's Industry Solution for VIP Interoperability
WILSONVILLE, Ore. and SAN JOSE, Calif. -- Jul 22, 2009 -- Mentor Graphics (Nasdaq: MENT) and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Accellera guide for verification IP (VIP) interoperability, currently in draft form, was enabled by technology contributions provided by both companies in open source form, and served as a basis for the reference implementation of the Accellera VIP Technical Sub-Committee (TSC) “Best Practices” guide. The guide provides recommendations for interoperability between verification components compliant with the Open Verification Methodology (OVM) and those developed using legacy methodologies such as the approach documented in the Verification Methodology Manual (VMM).
Historically, advanced verification users have had to invest a great deal of time and effort to develop verification environments with VIP from different sources. At the same time that the Accellera VIP TSC was framing the requirements for an interoperability solution, Cadence® and Mentor, working with leading customers, members of the OVM Advisory Group (OAG), and other industry participants, developed a set of library components fulfilling these requirements. This reference implementation was a key to validating the draft Accellera interoperability guide, which incorporates many portions of the documentation developed by Mentor, Cadence, and their OVM World partners.
“Our customers embraced the OVM very quickly when it was introduced two years ago, but communicated clearly that they wanted to include legacy VIP without having to re-write it from scratch,” said Dennis Brophy, director of strategic business development at Mentor Graphics. “We took a lead role in Accellera to define the industry requirements while working with our OVM partners to develop an interoperability solution. We are pleased to see the results of our efforts reflected in the draft guide that Accellera is in the process of making a standard.”
All aspects of the reference implementation are compliant with IEEE Std. 1800-2005 SystemVerilog and have been thoroughly verified using OVM 2.0.1 on the Cadence Incisive® and Mentor Questa verification solutions. The VIP interoperability approach documented in the draft Accellera guide enables users to integrate VIP written in standard IEEE verification and modeling languages and legacy methodologies. This minimizes the need to re-write existing VIP when setting up an OVM-based verification environment, a clear savings in cost and time to market for users.
“With our long history of support for SystemC models and e-based verification, our customers required a solution that spanned these two languages as well as SystemVerilog,” said Stan Krolikoski, group director, standards and ecosystem at Cadence. “Our leadership in the Accellera VIP TSC ensured that the scope of interoperability would span multiple languages and multiple methodologies. The OVM is robust enough to provide a complete solution for all of our customers, so we strongly support the draft Accellera interoperability guide and its recommended best practices.”
About the Open Verification Methodology
The Open Verification Methodology is the first open, language-interoperable, verification methodology in the industry. It provides a methodology and accompanying libraries that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The OVM and OVM World began in August 2007 as a joint effort by Cadence Design Systems and Mentor Graphics.
|
Cadence Design Systems, Inc. Hot IP
Cadence Design Systems, Inc. Hot Verification IP
Related News
- Accellera Members Approve VIP Standard Best Practices Guide, Continue Improving EDA Verification and Interoperability
- Accellera Forms Functional Safety Working Group to Standardize Data for Interoperability & Traceability in the Functional Safety Lifecycle
- Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
- Accellera Systems Initiative Acquires Open Core Protocol Standard and Infrastructure to Strengthen Interoperability in Electronic Standards Development
- STMicroelectronics, ARM and Cadence Improve Tool and Model Interoperability with Three Joint Contributions to Accellera Systems Initiative
Breaking News
- PLDA Announces XpressLINK-SOC CXL Controller IP with Support for the AMBA CXS Issue B Protocol
- TSMC Boosts Capital Expenditure Budget on Strong Outlook
- DCD With EBBM in USA & Greece
- Intel Appoints Tech Industry Leader Pat Gelsinger as New CEO
- Gartner Says Worldwide Semiconductor Revenue Grew 7.3% in 2020
Most Popular
- Gartner Says Worldwide Semiconductor Revenue Grew 7.3% in 2020
- TSMC to Kick off Mass Production of Intel CPUs in 2H21 as Intel Shifts its CPU Manufacturing Strategies, Says TrendForce
- Value of Semiconductor Industry M&A Agreements Sets Record in 2020
- Qualcomm to Acquire NUVIA
- BeagleBoard.org and Seeed Introduce the First Affordable RISC-V Board Designed to Run Linux
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |