Synopsys plans IP reuse tool
![]() |
Synopsys plans IP reuse tool
By Richard Goering, EE Times
March 10, 1999 (1:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990310S0010
MOUNTAIN VIEW, Calif. Synopsys Inc. is planning to release tools that facilitate the development and distribution of configurable silicon intellectual property (IP), according to discussions at the recent Intel Developer Forum. The yet to be named tools will leverage the graphical user interface technology that Synopsys uses to develop and deploy its own cores. Synopsys' PCI core is delivered with a graphical user interface that allows customers to configure the core, and generate synthesis scripts. Synopsys' upcoming NGIO core, announced at the Intel forum, will be created and deployed using the same technology. "It's like Adobe Acrobat in that there's both a developer side and a reader side," said John Chilton, general manager of the design reuse group at Synopsys, based here. "Any piece of IP built with the developer tool can be instantiated using the reader." He said the "reader" is currently planned for introduction at this month's IP99 Conference, while the "developer" is scheduled to appear at the June Design Automation Conference.
Related News
- STMicroelectronics and Synopsys Announce Partnership To Develop Industry-Standard Tool Platform for Design Reuse
- NSITEXE Successfully Develops Multiple Custom Processors for Automotive Applications in Half the Time with Synopsys ASIP Designer Tool
- Synopsys ASIP Designer Tool Speeds Development of Application-Specific Instruction-Set Processors for STMicroelectronics
- Synopsys Releases New Version of Coverity Static Analysis Tool with Enhanced Security for Mobile and Web Applications
- Toshiba Plans Deployment of Synopsys TetraMAX II on Upcoming SoC Design
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |