San Francisco -- July 27 2009 -- Agnisys Inc.
today announced IVerifySpec, a tool that ensures closure for Verification planning and execution. Using this tool and associated methodology, design/verification engineers and managers have a complete handle on the verification process. It eliminates the guessing game from hardware verification management. IVerifySpec keeps the focus on requirements while teams develop the verification plans, and execute the plan.
“Verification process is often an endless process. Progress is often measured in number of tests, duration of tests, or coverage matrix. This can lead the verification teams onto wrong paths and endless spirals where the verification effort is far removed from the business objective. With IVerifySpec, the design team, the verification team and the management, all have a clear understanding of what business purpose the verification effort is serving, this leads to a more focused team, better quality and faster time to market”, said Anupam Bakshi, CEO of Agnisys, Inc.
IVerifySpec brings together the requirements, the verification plan, the results of the verification process and the bugs, all in one document. In a pioneering use of the document editor as the interface, Agnisys has brought a new, innovative approach to requirement management. The tool and methodology have been deployed at several companies in US. About Agnisys, Inc.
Agnisys develops tools and provides services for the design of FPGAs, ASICs and Systems. Its’ mission is to bring high ROI design/verification products to market and provide exceptional services to its customers. It’s tool IDesignSpec has been recommended as a “Must See” by many industry analysts at the Design Automation Conference, in San Francisco, CA. Visit http://agnisys.us
for more details.