Atmel's System Designer 2.0 software tool suite provides software and hardware co-design and co-verification for FPSLIC- (field programmable system level integrated circuit) based embedded system designs. The FPSLIC family of programmable system-on-a-chip (SoC) processors integrates logic, processing, control, memory, and I/O functions.
The System Designer tool comprises a code development environment (compiler, debugger, and instruction set simulator), with a suite of FPGA design tools. The FPGA programmable logic and AVR microcontroller tool suites integrate with a co-verification environment that allows the FPGA and microcontroller portions of the design to be verified concurrently. The designer can see into the processor's program counter, memory, registers, and peripherals at every stage during HDKL simulation.
System Designer's HDL Planner module helps firmware developers create syntactically correct Verilog or VHDL designs for the embed ded FPGA logic inside the FPSLIC. Using a top-down design flow, the designer creates logic and memory components by means of more than 50 point-and-click function generators. HDL Planner generates architectural layout and post layout VHDL or Verilog models for the FPGA portion of the design.
System Designer includes C and assembly code modules that can be cut and pasted into the designer's application code for the fixed peripherals on FPSLIC, including two UARTs, three timer counters, two-wire serial interface, and programmable I/O ports.
System Designer is available now as part of the ATSTK94 FPSLIC Starter Kit, which can be licensed from $495.
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