Predictable Protocol Verification IP Solution Speeds Development Of Power Architecture-based Designs
SUNNYVALE, Calif. -- Sept. 16, 2009 -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced Denali's PureSpec(TM) verification IP support for IBM's PowerPC(R) processor local bus (PLB)-6, enabling verification of compliance with the latest PLB specification and validation of interoperability between the processor cores and integrated bus controllers. The high-quality, platform independent toolkits incorporates a set of IBM qualified solutions that provides a complete environment aimed to streamline Power Architecture(TM)-based and IBM CoreConnect(TM) designs.
"We work to insure our customers have access to best-in-class products in our ecosystem, such as Denali's PureSpec, a high-quality comprehensive verification IP solution," said Jim Cuffney, Executive Project Manager, PowerPC Cores Development at IBM Microelectronics. "IBM's collaboration with Denali gives designers the ability to quickly implement customized Power Architecture based applications in world-leading semiconductor technologies."
Denali suits its comprehensive PureSpec verification IP product with test-plan generation based on the protocol specifics and design parameters, seamless integration to verification methodologies (VMM, OVM, and eRM) and third-party planners enabling automated verification and back-annotation of the coverage data to the test plan.
"Our long-standing relationship with IBM, membership in Power.org, and delivery of comprehensive verification IP solutions continues to be a touchstone for enabling customer success," remarks David Lin, vice president of Marketing at Denali Software. "Our predictable protocol verification IP product for PLB-6 helps customers minimize risk and increase higher-quality IBM's CoreConnect(TM) on-chip bus and Power Architecture-based SoCs."
About Denali PureSpec
PureSpec is a predictable verification solution for protocol compliance and enables verification planning and coverage-driven verification closure. PureSpec verification solution includes a configurable bus functional model, protocol monitor, and complete assertion library for all components in the topology. PureSpec additionally provides an integrated data generation engine to help drive defined, pseudo-random bus traffic at all layers. A cumulative coverage database capability ensures that the overall test plan sufficiently exercises the design. For more product information, visit: www.denali.com/purespec.
About Denali Software
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.