LONDON Now that the SystemC language has reached a level of stability with the release of version 2.0, the Open SystemC Initiative (OSCI) is looking to further define its mission and create a set of working groups. The organization is shifting its focus to using the SystemC language for modeling systems.
SystemC has been criticized in some quarters as no more than a replacement for hardware description languages such as Verilog and VHDL.
Mike Bohm, chief scientist for HDL design at Mentor Graphics Corp., said SystemC is in position to become a systems modeling language as long as the right modeling styles and language constructs are in place.
"When I looked at the version 1.0 spec, it was more HDL synthesis," he said. "In that form, SystemC was limiting what the industry needs to go forward. We need a higher level, a behavioral level. Version 2.0 is starting to go down that path," Bohm said.
Kevin Kranen, president of OSCI, said, "With the version 2.0 core language, we believe everything you need to model a system down to hardware is in there. There is a general feeling that we want to extend the core language to model software.
"We want to be able to model multiple operating systems in a system environment," Kranen said. "We need to be able to model scheduling. But scheduling from a software perspective is different to scheduling from a hardware perspective."
Further extensions would be rolled into the core language, probably version 3.0, that is now the focus of one of the new working groups.
Kranen noted that there are other working groups. One, he said, has to do with libraries built on top of the core language for domain-specific purposes.
"Cadence and Philips want to add data flow modeling," Kranen said. "Adam Rose of Motorola in the U.K. is working on verification: How you model the stimulus of systems under test. And there are some nascent working groups. An analog group has not got off the ground yet but it is backed by FHT and Infineon."
Analog extensions to SystemC would mirror the efforts to add mixed-signal modeling to Verilog and VHDL in their respective AMS extensions.
"There are discussions about an API working group and about platform-based design," Kranen said.
The application programming interface issue in SystemC is complicated by the fact that there are two aspects to an API: one form would control the models, and another the core simulator, which forms part of the environment. The remaining group of the first batch tries to address the problem of bringing in existing models. "The IP [intellectual-property] integration group is being set up by Jon Connell of ARM. The aim is to look at how you take blocks of IP and make them accessible to a SystemC environment. It will address how you write a bus-functional model or an instruction set simulator," Kranen said. Bohm said methodologies to accompany the basic SystemC language would be vital.
"That"s what we did with VHDL and Verilog. Code after code looks identical out there. A lot of that has to do with style and methodology. We're going to be trying things out," Bohm said.
Kranen said the working groups would take on a lot of the methodology work.
"For example, the data flow group will share ideas on upper design flows, such as how you capture a data flow," Kranen said. "The benefit of an open-source environment like SystemC is that lots of people can use it to build models and create methodologies."
As a language, SystemC received a boost earlier this month with the decision by the last holdout against the language among the small community of C-modeling tools suppliers, Forte Design Systems Inc., to join OSCI.
Although the next major language changes will be in version 3.0, a parallel effort is under way to define fixes and small tweaks in the core language working group.
One remaining piece of organizational work that OSCI now has to do is to find out how to coordinate the working grou ps.
"The [OSCI] board is starting to form the cross-coordinating body. The steering group will work out how the groups can work together," Kranen said.
Chris Edwards is editor of Electronics Times, EE Times' sister publication in the United Kingdom.