Meylan, France -- October 12th, 2009 -- Embedded in an impressive number of System on Chips, the SYMPHONIE low voltage library includes sRAM, metal-programmable ROM and a standard cell stem.
Reducing the power consumption of a SoC is the modern challenge for SoC designers, reaching extreme requirements for RFID. Due to the double Gaussian curve of process demands, Dolphin Integration addresses the requirements of such applications with a dedicated SYMPHONIE low voltage library at 180 nm to be followed by its equivalent at 65 nm.
The SYMPHONIE library has the capability to operate at 1.1 V at 180 nm and includes:
- The patented Cassiopeia architecture with double-metal programming, dROMet; it features both low power and high density. The dROMet compiler offers flexibilities from 1 kilobit up to 1 Megabit.
- The Pluton architecture for sRAM, designed with a TSMC pushed-rule bit cell also ensures low dynamic power together with high density, for instances capacities between 512 bits and 512 kilobits. Migrating the implementation to the bit-cell of other foundries is performed on request.
- The patented SESAME LVLC stem, specifically designed to enable robust low voltage operation; its characterizations takes into account detailed physical phenomena linked to low voltage.
For more information about the SYMPHONIE library at 180 nm G process: http://www.dolphin.fr/flip/flip_lowvoltage.html
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs. For more information about Dolphin, visit: www.dolphin.fr/ragtime