Synopsys, ARM create design flow for core licensees

Synopsys, ARM create design flow for core licensees
By Michael Santarini, EE Times
November 20, 2001 (9:19 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0030

SAN MATEO, Calif. — Synopsys Inc. and ARM Ltd. have jointly created an RTL-to-GDSII reference design flow in an effort to help ARM's semiconductor licensees quickly create and harden custom variations of the ARM946-S synthesizable processor core.

ARM hopes the design flow will make life easier for its partners. For Synopsys, the flow represents a play to get big customers to buy not just a few point tools but the entire Synopsys tool flow.

The two have been working on the reference design for a year, said Rich Goldman, vice president of strategic market development at Synopsys. As part of the project, Synopsys has developed Synopsys Design Constraint scripts and optimized many of its existing tools. The resulting design kit and methodology, Goldman said, ensure that ARM silicon partners can quickly design variations of the ARM946-S core suited to their customers' needs .

"We have worked very closely with ARM to ensure that almost all Synopsys tools — especially Physical Compiler — are optimized for flows incorporating ARM cores," said Goldman. "Early customers using the flow have shaved weeks off their design time."

Simon Segars, vice president of engineering at ARM, said the Cambridge, England, company for many years has had a staff and tool suite dedicated to porting ARM cores to various semiconductor partners' processes. But now the chip partners want to be able to do it themselves.

"The good thing [about] delivering a hard core is that you know exactly what you are going to get," said Segars. "But porting and hardening cores is a complex task. We've built up in-house expertise and tools to facilitate this — to port a hard core and then characterize it. Over the last few years, silicon partners have been coming to us saying they want to change cache, which is very hard to do with a hard core."

With the Synopsys flow, he said, "our partner s can get the benefits of hard-core predictability, yet with the flexibility of a soft core."

Goldman said ARM designed the ARM946-S core using the RTL-GDSII reference design flow and hands the register-transfer-level version of the core to its semiconductor partners, which in turn are expected use the same reference design flow to harden it.

Classic optimization

The Synopsys contribution "speeds up the process and it allows the partners to optimize and customize the core," said Goldman. "Users can do classic optimizations like power, area or speed, but users can also do custom optimizations to adjust sizes of instruction or data cache."

Goldman said the flow also allows silicon houses to port the core to different processes. After the core is generated and targeted to the new process, they can pass customers the Primetime timing model and design view. "Silicon partners never pass off the GDSII," said Goldman. "This protects the IP [intellectual property], and ensures the end des ign is compliant with the ARM architecture. It has the flexibility of soft cores and the dependability of hard cores."

Goldman said the agreement is not exclusive and that ARM can work with other tool vendors and Synopsys with other core vendors.

The initial release of the tool flow includes Synopsys' Physical Compiler, Chip Architect, Design Compiler, DC Ultra, DesignWare, Power Compiler, Formality, DFT Compiler, TetraMAX, PrimeTime and VCS. The company hopes to incorporate Clock-Tree Compiler and Route Compiler, a detailed router, in the future. Those tools have yet to be released to the mass market.

Goldman said that customers can insert other vendors' point tools, because the tools in the flow are tied together using Synopsys Design Constraint, an open format. To get the scripts to work in another vendor's tools will likely require some amount of tweaking, however. Thus, Synopsys is encouraging ARM silicon partners to use Synopsys tools to get the maximum benefit from the reference design. < P> Goldman hinted that Synopsys and ARM not only plan to collaborate in the back end but may also be working in the system-level, hardware-software co-design areas.

"ARM will deliver the flow to their semiconductor partners, execute the flow and [offer] an implementation guide to help people through the flow," said Goldman. ARM also provides white papers describing the flow.