Fully Integrated Power-Efficient Flow Enables Fast, Easy Design of Low-Power Leading-Edge Devices
SAN JOSE, Calif., Oct. 29, 2009 – Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced that it has delivered a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI and SEHK: 0981.HK). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform.
“Power is now a critical design constraint, as important as timing and area from both a technology and cost standpoint,” said Max Liu, Vice President of the Design Services Center at SMIC. “The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.”
Validation of the flow was accomplished through implementation of low-power chips utilizing SMIC’s in-house–designed 65-nanometer libraries, including effective current source model (ECSM) standard cells, power management cells, PLLs, SRAMs and I/O libraries. Low-power technologies employed in the design include power gating and multi-supply/multi-voltage (MSMV) techniques to reduce leakage and dynamic power consumption.
“Power efficiency is a key requirement for many new semiconductors, yet designers sometimes think it’s too new and therefore too risky,” said Steve Carlson, vice president of product marketing at Cadence. “The Cadence Low-Power Solution provides a complete, silicon-validated front-to-back flow for designers targeting SMIC’s 65-nanometer process technology, including functional and structural verification, while increasing productivity. It’s fast, easy and proven.”
The SMIC 65-nanometer low-power Reference Flow 4.0 includes the Cadence Low-Power Solution, with Encounter? Conformal? Low Power, Incisive? Enterprise Simulator, Encounter RTL Compiler, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System and Encounter Power System.
Semiconductor Manufacturing International Corporation ("SMIC"; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 45nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, a 200mm fab under construction in Shenzhen, and an in-house assembly and testing facility in Chengdu. SMIC also has customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 200mm wafer fab in Chengdu owned by Cension Semiconductor Manufacturing Corporation and a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.smics.com .
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.