Noesis Technologies releases ITU G.704 E1 Framer/Deframer IP core
November 3, 2009 -- Noesis Technologies announced today the immediate availability of its ITU G.704 compliant E1 Framer/Deframer IP core (ntE1_G704).The IP core is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.163. The core provides all the necessary data formatting transforms for transmission over an E1 carrier. E1 is one of the two most widely used TDM (time division multiplexing) carriers incorporating 32 channels, each with a bandwidth of 64 kbps providing a total bit rate of 2048 kbps.
The ntE1_G704 IP core provides a flexible interface supporting hardware and microprocessor modes. Specifically the core can be connected to a host system either through an 8-bit parallel microprocessor interface (HP mode) or through a set of I/O ports (HW mode). When in HP mode, the microprocessor configures and monitors the functionality of the core through a rich set of registers. When in HW mode, the core is directly controlled and monitored through a set of dedicated ports and no microprocessor control is necessary.
At the transmit side, the framer generates framing patterns, CRC4 bits, formats outgoing and signalling data, generates alarms and clock outputs for data conditioning and decoding. At the receive side, the deframer establishes frame / multiframe synchronization, extracts data, signalling and alarm flags. It provides information like frame, multiframe alignment, calculates CRC4, counts CRC4 errors and performs A-bit processing.
The ntE1_G704 core can be used in primary rate digital trunk interfaces, computer to PBX interfaces (CPI and DMI), to any high speed computer-tocomputer data link and generally to any digital cross connect interface.
License options and availability
ntE1_G704 is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.
About Noesis Technologies
Noesis Technologies is a leading provider of telecom IP core solutions. Noesis Technologies specializes in the design, development and marketing of high quality, cost effective communication IP cores and provides VLSI design services. Its field of expertise include Forward Error Correction, Cryptography and Networking technology. In these fields, a broad range of high quality IP cores are offered.
Noesis IP cores have been licensed worldwide and its impressive list of customers ranges from large companies to dynamic startups in diverse market sectors such telecommunications, networking, military, industrial control and lower-power portable.
For more information and detailed datasheets please email your request at info@noesis-tech.com
|
Noesis Technologies Hot IP
Related News
- Noesis Technologies releases its Ultra High Speed FFT/IFFT processor IP Core
- Noesis Technologies releases its XTS mode AES processor IP Core
- Noesis Technologies releases a fully configurable FFT/IFFT processor
- Noesis Technologies releases fully configurable N-point FFT/IFFT core
- Noesis Technologies releases NIST FIPS-197 compliant Low Power AES IP core
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |