Actel Expands RTAX-DSP FPGAs with New Configurable DSP IP Cores

Actel's highly configurable DSP IP cores provide easy implementation of complex DSP functions within RTAX-DSP Space-Flight FPGAs

MOUNTAIN VIEW, Calif., November 18, 2009 — Actel Corporation (NASDAQ: ACTL) today announced several highly configurable DSP IP cores expanding the design creation capabilities for the RTAX2000D and RTAX4000D DSP FPGAs. The new cores enable designers to easily create common DSP functions such as filters (FIR, IIR) and transforms (FFT, IFT, DCT). Using a graphical user interface (GUI) embedded in Actel's Libero® Integrated Design Environment (IDE), the cores are targeted to RTAX-DSP space-flight FPGAs.

"By providing a simple but powerful user interface, these configurable DSP cores greatly simplify and shorten the design cycle for DSP applications targeting our new RTAX-DSP FPGAs for space-flight applications," said Ken O'Neill director, high reliability product marketing at Actel. "These new offerings expand the horizons of the RTAX series of FPGAs, which already have a well-established space-flight track record."

Actel's DSP IP Cores

The three new cores are supported through comprehensive software dialog windows allowing for the quick selection and configuration of multiple common DSP functions.

• Multiplier
• Multiplier with Adder or Subtractor
• Multiplier with Accumulator

The configurable DSP IP cores generate structural netlists in either Verilog or VHDL and can be easily instantiated into a complex RTAX-DSP FPGA design using Actel's Libero IDE and SmartDesign graphical block system design creation tool. Comprehensive handbooks are available to assist designers in building various DSP functions.

The IP cores take advantage of the embedded mathblocks available in RTAX-DSP devices. Each mathblock contains a fast 18-by-18 bit hardware multiplier, plus a 41-bit internal adder-subtractor and register that can be configured for accumulating multiplier results. The multiplier can be broken into two 9-by-9 multipliers when less precision and more multipliers are needed. A number of different pipelining options are available, with optional registers on all inputs and outputs. Mathblocks have cascade outputs and inputs so, for common applications like FIR filters, they may be chained for maximum performance, leaving FPGA fabric resources free. RTAX-DSP devices have up to 120 mathblocks, each of which can perform full-precision multiplications at up to 125 MHz and has built-in protection against radiation-induced single event upsets (SEU) and single event transients (SET).

Availability of the new IP cores marks another milestone in the introduction and support of the RTAX-DSP FPGA product family, which merges enhanced signal processing capabilities with the tried-and-trusted technology of the underlying RTAX architecture and process. This underscores Actel's commitment to provide designers of space-flight systems with the performance and reliability they need.

Pricing and Availability

The cores are available immediately and are included with an Actel Libero IDE Platinum software license, priced at $2495 per seat. Node-locked and floating licenses are available.

About Actel

Actel is the leader in low-power FPGAs and mixed-signal FPGAs, offering the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com.

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