Tokyo -- November 30, 2009 -- Renesas Technology Corp. today announced that it is sampling the SH-Mobile Application Engine 4 (SH73720), an ARM® Cortex™-A8 *1 based application engine running at maximum 1GHz, targeted for next generation mobile phone and mobile device implementations. With the integration of various dedicated processing engines the device features ultimate multimedia capabilities, such as full HD 1080p video recording, playback at 30fps, and high speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience. Leveraging on Renesas' market proven Image Signal Processor (ISP) technology, the SH-Mobile Application Engine 4 provides a state-of-the art 16Mpixel ISP for best visual quality while supporting full HD 1080p movie processing. Fabricated in Renesas' optimized 45nm low power process and integrating a wealth of new and innovative power saving schemes, it exceeds the stringent power budget requirements of mobile phones.
“With broadband wireless access like UMTS/HSPA or LTE, customers can have the Internet at their fingertips wherever and whenever. Access to music, videos and games with mobile phones becomes as simple as it became on the PC a few years ago” says Shinichi Yoshioka, General Manager of System Solution Business Unit2, System Solution Business Group, Renesas Technology Corp. “Renesas has developed the SH-Mobile Application Engine 4, as the first device of the SH-Mobile Application Engine Series in a new class of application processors to offer an entirely new user experience on mobile computers and to solve the conflicts around creating an exciting multimedia experience within the low power budget of mobile devices.”
The SH-Mobile Application Engine 4 is based on an ARM® Cortex™-A8 core operating at maximum 1GHz. Leveraging Renesas' vast experience of highly integrated SoC systems, a competitive SoC process and an innovative design architecture, this device aims for one of the industry's most efficient ARM® Cortex™-A8 implementations providing amble processing performance for next generation applications while pursuing the ultimate low power consumption that enables an entirely new user experience on mobile devices.
For the ultimate multimedia experience the SH-Mobile Application Engine 4 incorporates a variety of dedicated processing engines. An integrated ISP supports 16M pixel still images and full HD 1080p movie images. A dedicated high-performance multi-codec video processing unit for ultra-low power video processing enables the device to support full HD 1080p multi-standard video use cases such as encoding (recording) and decoding (playback) of full HD 1080p video at 30 frames per second (fps). Combined with various multi-phased visual engines, such as IP for edge enhancement or median filtering, the realization of high quality HD images and videos reaches levels which consumers will not have experienced before on mobile devices.
To support high speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience, the device is equipped with a powerful POWERVR SGX *2 3D graphics engine, licensed from Imagination Technologies, supporting graphic APIs such as OpenGL *3 ES1.1/2.0 and Open VG. *3
To round off the multimedia experience, the SH-Mobile Application Engine 4 also incorporates a highly sophisticated audio subsystem enabling well over 100 hours of audio playback on a standard mobile phone battery.
For design flexibility and reduced system BOM, the SH-Mobile Application Engine 4 includes a wide variety of on-chip peripheral functions and connectivity interfaces. This includes two USB 2.0 Host/Function modules (with high-speed data transfer mode support), three SD host controllers with support for high-speed data transfer mode and a 24-bit TFT color LCD controller supporting up to WXGA+ display sizes. Furthermore a PAL/NTSC encoder and an HDMI transmitter are integrated together with a complete HDMI v1.3a & CVBS TV-Out interface.
The SH-Mobile Application Engine 4 is packaged in a 0.4mm pitch, 12mm × 12mm BGA package that allows package-on-package vertical stacking of low power, multiple chip package (MCP) memory such as LP DDR2, greatly reducing the overall footprint of the memory and processor combination.