Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Version 8 Development Tools Improve Design Automation for Faster Development Time and Greater Ease-of-Use
SANTA CLARA, Calif. - December 7, 2009 - Tensilica Inc. today announced its eighth generation tools that further automate customized Xtensa dataplane processor (DPU) design and speed software development. Improvements cover improved compiler technology, better multi-core system simulation and profiling, an upgraded integrated development environment (IDE), and pin-level co-simulation with RTL. These enhancements further strengthen Tensilica's leading position as the highest performance, and most complete, customizable processor core solution for SOC (system-on-chip) designs.
"In the dataplane - as opposed to the control plane - our DPUs have to deal with intensive data processing workloads and direct interconnection to hardware blocks," stated Steve Roddy, Tensilica's vice president of marketing and business development. "With this eighth generation tool set, we've concentrated on improvements that make it easier for designers to use customized DPUs to perform these data-intensive tasks, bringing programmability, enhanced debugging, and post-silicon software upgradability to signal processing and other dataplane functions previously handled in dedicated hardware blocks."
Custom Data Types
Tensilica's compiler now supports operator overloading on custom data types in the 'C' programming language, without any of the overhead that is often associated with it. The compiler also now displays custom data types in their natural format for faster debugging.
Tensilica is well known for its ability to let designers add custom instructions and data types to its processors to improve performance. If an application needs to work on 56-bit data, a designer can now define a custom 56-bit data type with a single line of code. The designer can also specify what regular 'C' operators, such as '+' and '*', should do when using this data type. The overloading is always done with zero overhead so the resulting binaries are most efficient.
Porting and creating 'C' application code that uses custom data types is now much easier because standard 'C' operator syntax can be used. This makes the code easy to read and simpler to port via changes in the 'C' header files rather than throughout all of the source code itself.
New User-Defined Display Formatting (UDDF) provides a simple means for the user to display non-integer data types (such as fixed point and vectors) in a more natural and readable way that makes debugging issues much faster.
Custom data types that are pre-defined in Tensilica's audio and communications DSPs, such as HiFi and ConnX D2, already have overloading definitions and pre-defined UDDFs so these benefits can be seen out-of-the-box.
Multi-core System Programming, Simulation and Profiling
Tensilica now allows designers to program, simulate and profile a simple shared memory subsystem for heterogeneous cores quickly within the Xtensa Xplorer
IDE. The memory partitioning for each core and the shared memory is simplified by specifying them in the new subsystem wizard. With a subsystem defined, it can be simulated and profiled within the IDE for initial assessment of hardware and software partitioning using side-by-side profile comparisons.
To aid the designer in dealing with shared memory systems, Tensilica provides a new synchronization library in 'C' source form with primitives for locks, barriers, and semaphores. With this library, up to six man-months of development and bug fixing can be avoided for designers who are new to shared memory systems.
Improved Integrated Development Environment
Tensilica made several improvements to its Xtensa Xplorer IDE so designers now have an upgraded IDE platform (Eclipse 3.3, CDT 4.0) as well as faster simulation speeds and more efficient debugging.
Pin-Level System-C CoSimulation with Verilog
Additionally, Tensilica has deepened its simulation capability with the introduction of a new link between its pipeline-accurate, cycle-accurate Xtensa Instruction Set Simulator (ISS) and the leading Verilog simulators. Designers can now run pin-level accurate System-C simulations of Tensilica DPUs in their native Verilog simulators. (See companion news release - Top EDA Companies Endorse Tensilica's Pin-Level SystemC Models )
Tensilica's newest generation processor design and software development tools are available now.
Tensilica, Inc. - the leader in customizable dataplane processors - is a semiconductor IP licensor recognized by the Gartner Group as the fastest growing semiconductor IP supplier in 2008. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific dataplane performance targets. Tensilica's DPUs power SOC designs at system OEMs and five out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.