HENDERSON, Nev.-- December 21, 2009 --Aldec Corporation, a leader in RTL Simulation and Electronic Design Automation (EDA), releases its latest RTL and gate-level simulator, Active-HDL™ 8.2 sp1, for FPGA design and verification engineers. Active-HDL 8.2 sp1 includes full support for Xilinx® SecureIP, IEEE VHDL/Verilog® encrypted IP and an enhanced Assertions bundle option. The new Assertion bundle supports three Assertion types: IEEE 1800 SystemVerilog Assertions (SVA), Property Description Language (PSL) and Open Vera Assertions (OVA) for legacy designs. The bundle also supports a dedicated Assertions Viewer, Assertion debugging and complete visibility of Assertions, properties and Functional Coverage statements through the simulator.
Active-HDL 8.2 sp1 is available today and is sold directly from Aldec and its authorized world-wide distributors. For more product information, visit http://www.aldec.com/products/active-hdl. To download a free 20 day evaluation copy today, please visit http://www.aldec.com/Downloads/default.aspx.
Active-HDL is a brand-leading Windows® FPGA design and simulation solution. The product includes: an HDL Design tool suite, high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for Actel®, Altera®, Lattice®, Quicklogic® and Xilinx® FPGAs and more than eighty popular EDA tools, in a single environment. Active-HDL supports Windows® 7, Vista, XP and 2003, 32-bit and 64-bit operating systems.
Aldec Corporation is an industry-leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. Aldec is a privately held corporation and employs approximately 200 people worldwide.