Tool vendors Synplicity Inc. and Forte Design Systems Inc. bring system-level tools to PLD masses

Pair brings system-level tools to PLD masses
By Michael Santarini, EE Times
November 19, 2001 (10:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011119S0025

SAN MATEO, Calif. — Tool vendors Synplicity Inc. and Forte Design Systems Inc. this week will launch what they call the first system-level design and verification flow for programmable logic device (PLD) designers.

Programmable logic designers can use Forte's GigaScale design and verification suite with Synplicity's Synplify Pro RTL synthesis tool to synthesize C++ code into a gate-level netlist for all the products now supported by Synplify Pro, said Joe Gianelli, director of business development and strategic alliances at Synplicity.

"Synplicity has been examining various C platforms for the last year and a half and decided to work with Forte as more and more customers are starting to look at their technology," said Gianelli. "FPGA devices are evolving into system-level components now that many will contain microprocessors. We feel this is a step users are going to be taking and the leading-edge d esigners are already looking for system-level tools. We believe we are the first on the market with a solution."

The Cynthesizer lets users integrate system-level models, hardware models, software models and then does verification for all the models, said Brett Cline, vice president of marketing at Forte.

Close to RTL

Cline said users create an executable spec or model in the CynLib language that describes users' systems and lets them simulate and verify the functionality at a level higher than RTL.

Users then refine the model until it becomes what Cline described as "something close to RTL." Forte and Synplicity worked together so that Cynthesizer C++-to-HDL now understands Synplify Pro directives. This allows the user to direct Synplify Pro from Cynthesizer to create gates specific to a particular PLD. The netlist can then be read by a given programmable logic vendor's place and route tool, which will then program the PLD.

The agreement could turn out to be a springboard for Forte, allowing it to jump into the expansive PLD user market. Previously, Forte's GigaScale suite solely targeted ASIC and system-on-chip (SoC) designers cutting their teeth on new system-level design methodologies and tools.

Altera Corp. is engaged with both Synplicity and Forte to ensure the flow works with Altera's tools and supports Altera's system-on-programmable chips, such as Excalibur, said Tim Southgate, vice president of software and tools marketing at Altera.

"We have been a firm believer that a better language for describing systems is necessary," said Southgate. "Chips are now available that give you both a processor and programmable hardware on the same device, and we are looking for a good practical, robust system that can take a system architect at a higher-level language such as C and get it into our parts. This collaboration is very appealing. Synplicity is providing proven implementation and knowledge of programmable devices and Forte is providing a robust front end."

Gianelli said that Synplicity has talked with other vendors and considered other system-level languages such as SystemC and is not exclusively endorsing Forte's Cynlib. But Cline said that his company believes that somewhere down the road CynLib and Open SystemC will merge anyway. "I'm sure Synplicity and Altera will support whatever standard emerges," Cline said.

Synplicity and Forte said the combined tools will work with any FPGA vendor's device family so long as it is supported by Synplify Pro.

Synplicity's Synplify Pro, starting at $19,000, comes with an optimized interface to Forte's Cynthesizer software. Current customers on maintenance will be upgraded free.

Forte's GigaScale design and verification products start at $40,800. The Cynlib, C++ class library is available for free under an open-source license.