WILSONVILLE, Ore., January 25, 2010 – Mentor Graphics Corp. (NASDAQ: MENT) today announced that the Catapult® C Synthesis tool has added SystemC synthesis, expanding the Catapult C tool’s full-chip synthesis capabilities. This complements the Catapult C tool’s existing algorithmic, control logic, and low power synthesis capabilities and expands its full-chip synthesis application scope through the efficient handling of specific SoC needs such as complex bus interfaces, SoC interconnect and TLM2.0-based ESL flows.
Catapult C support for SystemC source descriptions augments its existing support for ANSI C++ input, allowing high-level synthesis users to choose the industry standard high-level synthesis language that best suits their company’s methodology. The Catapult C tool now supports SystemC cycle-based descriptions, and goes beyond traditional solutions by also offering support for transaction-level synthesis.
Dual Language Support Ideal for Full-Chip High-Level Synthesis Methodology
In addition to its well established support of abstract source descriptions in pure untimed ANSI C++, the Catapult C tool now offers an extra level of modeling granularity with cycle-accurate SystemC. This unique dual language approach offers designers a wide range of modeling and synthesis options. The Catapult C tool users now have the ability to express complex interface protocols, such as those found in SoC bus interconnects, using a timed SystemC source while keeping the rest of the design functionality in pure untimed ANSI C++. Designers can also express structure and hierarchy either by using SystemC modules or by inferring them from natural C++ boundaries; such as functions, loops or scopes. The result is a standards-based method where legacy synthesizable SystemC models can easily be leveraged in the Catapult C environment, as well as linked with untimed ANSI C++ sources.
Mentor did not stop with support for timed SystemC as is prevalent in existing SystemC high-level synthesis tools, but also added support for abstract SystemC FIFO communication and TLM-based ESL flows, matching high-level synthesis with ESL practices. Traditionally, SystemC synthesis tools have forced designers into a coding style based on clocks and signals. However, transaction-level modeling has emerged as the most widespread way of using SystemC. Recent surveys indicate that 80 percent of today’s SystemC users favor working on transactional models above the cycle accurate level, and today most ESL activities, such as architecture analysis and virtual prototyping, rely on TLM. By supporting a modeling style compatible with the OSCI TLM2.0 approach, the Catapult C tool offers strong ties with ESL flows, methods and tools—such as the Mentor Vista™ platform—for comprehensive ESL design, verification and synthesis.
“Mentor's decision to add SystemC support to a proven high-level synthesis flow with Catapult C synthesis is very welcome,” said Takashi Hasegawa, Deputy General Manager, SoC Solutions Division, Common IP & Technology Development Unit, Fujitsu Microelectronics Limited. “We’ve made efforts for a long time for the standardization of SystemC, and also anticipate that this addition will enable us to handle an even broader range of application challenges and provide more flexibility in using Catapult C with Fujitsu supplied silicon technology libraries for our mutual customers.”
“Mentor’s Catapult C tool provides the right balance between detail and abstraction of advantage by dual language. Its cycle-accurate SystemC support gives us fine-grain control over our design and ability to read legacy synthesizable SystemC IP, while its unique support for SystemC-TLM provides the abstraction missing from other HLS tools,” said Yoshinao Umeda, President, PRIMEGATE Ltd. “We are confident that Catapult C will have a positive impact on not only our business, but also most of electronic and automotive businesses, and help our customers experience more success with their ESL flows.”
“By expanding the Catapult C tool’s high-level synthesis language support to include both ANSI C++ and SystemC, Mentor is demonstrating its continuing commitment to standards and interoperability,” said Simon Bloch, Vice President and General Manager of the Mentor Graphics Design and Synthesis Division. “In particular, the convergence of SystemC TLM and high-level synthesis will enable the semiconductor industry at large to move up in abstraction and make strides in improving overall design productivity.”
The Catapult C Synthesis tool automatically generates control and algorithmic RTL multi-block designs from pure ANSI C++ and SystemC sources. This process gives designers time and freedom to automatically perform detailed design exploration and quickly achieve fully optimized and error-free hardware implementation. By accelerating time to verified RTL without sacrificing quality of results, Catapult C provides the productivity boost required to tackle the design and verification challenges of modern ASIC design. Catapult C has been recognized as the High Level Synthesis market leader by Gary Smith EDA for 3 years in a row.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.