MoSys Expands Business Model to Fabless Semiconductor and IP
SUNNYVALE, Calif.-- February 02, 2010 --MoSys, Inc. (NASDAQ: MOSY), a leading provider of differentiated, high-density memory and high-speed interface (I/O) intellectual property (IP), today unveiled a roadmap for its new Bandwidth Engine™ integrated circuit (IC), which will combine MoSys' patented 1T-SRAM® high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology and an arithmetic logic unit (ALU). MoSys' Bandwidth Engine promises to deliver unparalleled bandwidth performance in next-generation networking systems for storing, manipulating and accessing packets, control information and statistics at breakthrough rates. In conjunction with the announcement of this new product initiative, MoSys also today announced the expansion of its overall business model to become a fabless semiconductor company supplying high-performance ICs, in addition to differentiated IP.
For the past several years, processor performance in applications such as computing and networking has continued to nearly double every 18 months. During the same period, the performance of memory technology has not kept pace, creating a significant barrier to improving overall system performance. The Bandwidth Engine family of ICs represents a breakthrough for next-generation networking systems. The combination of the high-speed random access of a 1T-SRAM memory core with a serial I/O operating at 10 Gbps will enable a Bandwidth Engine device to provide up to two billion accesses per second, over twice the performance of designs utilizing memory technologies. To further boost system performance, the on-chip ALU will allow macro functions to be performed within the Bandwidth Engine, reducing iterations between the other packet processing ICs and a Bandwidth Engine.
MoSys expects the Bandwidth Engine to enable up to four times the throughput, two to four times the density, up to 40 percent lower power and system cost savings of up to 50 percent compared with today’s alternative solutions. MoSys expects to offer samples of the first Bandwidth Engine ICs in late 2010, with production quantities available in the second quarter of 2011.
Complementary to Bandwidth Engine, MoSys is also introducing the GigaChip™ Interface, an open, CEI-11 compatible chip-to-chip interface to enable highly efficient serial chip-to-chip communications in high-speed networking systems. The Bandwidth engine ICs will feature the easily-implemented GigaChip Interface, which will be designed to achieve 90 percent payload bandwidth efficiency. MoSys is currently working with partner companies to create an ecosystem that will support the GigaChip Interface. More information about this open interface will be available in the weeks and months ahead.
“When I returned to MoSys in late 2007, it became clear to me that our 1T-SRAM, with its advantages of up to three times the density of traditional SRAM technology, fast random access and high reliability, is a perfect solution to address the need for a dramatic increase in bandwidth in next generation switching and routing applications,” said Len Perham, President and CEO of MoSys, Inc. “However, it was also clear that increasing bandwidth performance would require a new generation of high speed serial I/Os. The potential of such a solution was so great that it led to our acquisition of Prism Circuits last year, which, in addition to expanding the available market in our IP business, also brought MoSys the world class I/O engineering team and the SerDes technology required to support the Bandwidth Engine family of products today and into the future.
“I believe that becoming a fabless semiconductor company will substantially strengthen our competitive position and dramatically increase our total available market. We estimate that the annual market for our Bandwidth Engine family of products will be substantial and will provide a strong foundation for long-term growth and value creation at MoSys. We remain firmly committed to our IP business and believe that it will contribute significantly to our growth, as differentiated IP is highly synergistic with our future semiconductor product plans. We plan to continue to deliver differentiated IP to the market in the form of IP blocks that customers can integrate into their SoCs.”
MoSys will formally announce its Bandwidth Engine, the GigaChip Interface and its expanded business model at a press conference on February 2, 2010, at 9 a.m. PST in Santa Clara, California. The press conference will be webcast live and a replay will be made available after the event on the MoSys website. A link to the webcast is available at http://www.mosys.com/investors.php?page=pressRoom.
About MoSys, Inc.
MoSys, Inc. (NASDAQ: MOSY) develops serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs. MoSys’ IP portfolio includes DDR3 PHYs and SerDes IP that support data rates from 1 - 11 Gigabits per second (Gbps) across a variety of standards. In addition, MoSys offers its flagship, patented 1T-SRAM® and 1T-Flash® memory cores, which offer a combination of high-density, low power consumption, high speed and low cost advantages for high-performance networking, computing, storage and consumer/graphics applications. MoSys IP is production-proven in more than 225 million devices. MoSys is headquartered in Sunnyvale, California. More information is available on MoSys' website at www.mosys.com.