Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Performance Improvements Up to 3x Over ConnX Baseband Engine Introduced in June 2009
SANTA CLARA, Calif. - February 8, 2010 - Tensilica, Inc. today introduced ConnX BBE16, its second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. ConnX BBE16's 16-way MAC (multiply accumulator) architecture is optimized for the most demanding wireless DSP (digital signal processing) tasks, including OFDM (Orthogonal Frequency-Division Multiplexing) algorithms and FFT (Fast Fourier Transform), FIR (Finite Impulse Response), IIR (Infinite Impulse Response), and matrix computation. It is fully optimized for size and power-sensitive applications, and provides up to three times the performance of the original ConnX BBE on some of these critical algorithms. This architecture is particularly suited for system-on-chip (SOC) designs for programmable radio handsets, low-cost femto-cell and pico-cell base stations, micro and macro base stations, digital media broadcast receivers, and multi-format mobile DTV (digital television) demodulation.
Tensilica introduced its first ConnX Baseband Engine (BBE) in June of 2009. Tensilica has licensed ConnX BBE to several customers and it is already in volume production. Based on customer feedback, Tensilica developed its next generation DSP: the ConnX BBE16. ConnX BBE16 was developed in record time, leveraging the Tensilica Xtensa® customizable processor foundation technology.
"The wireless industry is on a fast track to continuously improve the bandwidth and quality of service to reliably handle the huge increase in wireless data traffic. This requires a constant evolution from 3G to HSPA+, LTE and 4G networks while reducing the overall power budget both in handsets and base stations," stated Jack Guedj, Tensilica's CEO. "Designers of next-generation equipment are looking for a more programmable solution so they can quickly evolve their handsets or networks to support the evolving standards. The ConnX BBE16 gives designers a power-efficient, programmable platform which accelerates time to market."
An Extremely Efficient Architecture
The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units.
Enhancements to the ConnX BBE16 DSP include an improved instruction set with added support for:
- Matrix multiplication
- Real and complex FIR filters, including both symmetric and non-symmetric filters
- Polynomial approximations, especially for trigonometric and transcendental functions
- Key wireless functions such as polynomial generation and multiply-accumulate for de-spreading functions (up to 16 complex code MACs/cycle)
- High precision FFTs with adaptive range management
- Expanded support for vector normalization, shifts and packing
The ConnX BBE16 can achieve 17 GB/s memory bandwidth at 550 MHz. Other performance metrics include: 16 multiply adds per cycle; four complex FIR taps per cycle; and one Radix-4 FFT butterfly per cycle. The improvements result in a 3x speed up on small matrix multiplications, a 20 percent speed up on complex FIR filter performance, and 2x speed up on polynomial approximations.
Designed for Easy Programmability
The ConnX BBE16 is fully programmable in C, and comes with a complete, proven optimizing compiler and software tool set. Easy programmability, including automatic vectorization for ANSI C programs and optimized instructions for fast complex FFT, FIR, IIR, and complex matrix operations, make this new architecture ideal for quick implementation. To further speed the programming effort, optimized DSP kernel libraries are available for the ConnX BBE16 with functions ranging from generic DSP functions to specialized DSP kernels.
The ConnX BBE16 is a click-box configuration option with the configurable Xtensa LX3 processor core, so designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The product and an evaluation kit will be available in the second quarter of 2010.
Tensilica, Inc. - the leader in customizable dataplane processors - is a semiconductor IP licensor recognized by the Gartner Group as the fastest growing semiconductor IP supplier in 2008. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific dataplane performance targets. Tensilica's DPUs power SOC designs at system OEMs and five out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.