PAClib enables rapid, predictable specification for optimal power/timing/area/throughput
Waltham, Mass. – February 9, 2010 - Bluespec Inc. today announced its Pipelined Architecture Composers library (PAClib), the industry’s first parameterized, plug-and-play building block library for specifying, modeling and synthesizing algorithm and datapath designs.
PAClib consists of a set of standard pipeline building blocks, user parameterized by computational functions, structures, buffering and data types. Providing 100% transparency and control of architectures, PAClib enables the rapid creation of a single algorithm specification that can generate many different micro-architectures for rapid architectural exploration – and correct control-logic is automatically generated for each micro-architecture. PAClib can be seamlessly integrated and mix-and-matched with high-level complex control, so that designs of any size and complexity can be specified, and considerations such as memory accesses and data movement can be easily and efficiently incorporated in the same design.
Though C/C++/SystemC approaches can get to initial RTL quickly, meeting price, performance and power specifications can be a significant challenge. Achieving good quality of results often requires a ‘long tail’ of effort, including the extensive massage of both source code and constraints in non-transparent and tool-specific ways, which can further limit portability and maintainability. In contrast, because hardware designers get the same transparency and control of architecture to which they are accustomed, the PAClib library enables predictable, consistent and rapid achievement of design specifications.
“PAClib is a terrific example of the power of Bluespec atomic transactions and extreme parameterization, representing the industry’s first use, for synthesis, of features found in the world’s most advanced programming languages,” said Rishiyur S. Nikhil, CTO of Bluespec, Inc. “As it is not built-in, PAClib is available in source-code form, making it fully extensible and modifiable for customer use.”To learn more, please contact Bluespec or register to download the free technical whitepaper entitled, “High-level ‘plug-and-play’ specification, modeling and synthesis of pipelined architectures with Bluespec’s PAClib”, which includes a case study showing IFFT in 100 lines of code, generating 24 micro-architectures for FPGAs and ASICs. The whitepaper is available at: http://www.bluespec.com/algorithmic-synthesis.htm
Bluespec provides the only general-purpose, high-level synthesis toolset for any use model (models, testbenches, production IP) and design type (datapath, control, interconnect). Models and testbenches can be synthesized along with legacy IP to leverage emulation much earlier in the development cycle. Users get better chips to market sooner by developing software in parallel and validating architectures well before tapeout. Bluespec is the only synthesis tool built on atomic transactions, proven technology for managing and simplifying large-scale hardware concurrency. More information can be found on www.bluespec.com or by calling (781) 250-2200.