MOUNTAIN VIEW, Calif. – Feb. 22, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced the availability of Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. These Jasper Proof Kits are sets of properties, written in SystemVerilog, related to standard JEDEC interface protocols. Each Proof Kit includes a Formal Testplan providing detailed instructions on verifying DDR designs, plus properties for the protocol that the JasperGold® Verification System can prove against designs employing the standard. LPDDR solutions are experiencing high growth in mobile and embedded markets as demand for the low-power parts surges.
“These new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards,” said Lawrence Loh, Jasper Vice President of Worldwide Applications Engineering. “They join our existing Proof Kits for SDR, DDR and DDR2, and we continue to actively follow and support new standards as they emerge.”
The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.