Tensilica Introduces Third Generation Diamond Standard Controllers Optimized for Low Power, High Performance Applications

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Up to 15% Improvement in Speed/Power Performance and 20% Smaller Size

SANTA CLARA, Calif. - March 15, 2010 -Tensilica,  Inc. today introduced its third generation of Diamond Standard controllers. This family of five upward-compatible processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today's compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15 percent faster clock speed, up to 20 percent smaller die area and up to 15 percent less power consumption.

"The Diamond processor family provides our customers with significant improvements in speed/power performance in the widest range of fully compatible 32-bit controllers in the industry," stated Steve Roddy, Tensilica's vice president of marketing and business development. "These deeply embedded control cores can also serve as a starting point for customization of a tailored Xtensa dataplane processor (DPU) for designers looking to incorporate additional control or signal processing capability."

A Broad Family with a Wide Range of Capabilities

The Diamond Standard family of cores includes:

• The ultra-low-power Diamond 106Micro, a small cache-less controller with memory protection, an iterative 32x32 multiplier, 15 interrupts, an integrated timer, and on-chip debug hardware that achieves Dhrystone 2.1 results of 1.22 DMIPS/MHz.
• The small Diamond 108mini, which adds a 32-bit integer divider, dual local data RAMs, 22 interrupts, three integrated timers, and dual 32-bit GPIO (general-purpose input/output) ports and achieves Dhrystone 2.1 results of 1.34 DMIPS/MHz.
• The powerful Diamond 212GP, which adds data and instruction caches and 16-bit DSP instructions and achieves Dhrystone 2.1 results of 1.38 DMIPS/MHz.
• The Diamond 233L, which has the same features as a Diamond 212GP and adds a Memory Management Unit (MMU) optimized for Linux operating systems.
• The ultra-high-performance Diamond 570T, which is a three-issue VLIW (very long instruction word) core with dual 32x32 MULs and 16 Kbyte, 2-way set associative instruction and data caches, which achieves Dhrystone 2.1 results of 1.59 DMIPS/MHz.

Designed for Easy SOC Integration

The Diamond Standard processors were designed with easy SOC (system on chip) integration in mind. All of the Diamond controllers are available with support for AMBA AHB-Lite and AXI bridges with asynchronous or synchronous clocks. In addition, on the Diamond 108Mini, 212GP, and 570T, designers can bypass the system bus altogether in order to achieve much higher input/output I/O bandwidth and seamless integration with RTL via direct GPIO connection interfaces for data and system monitoring and control. The Diamond 570T also provides 32-bit FIFO interfaces for direct data I/O (input/output) interface with other system blocks without using the system bus.

Availability

The Diamond Standard processors are available now.

About Tensilica

Tensilica, Inc. - the leader in customizable dataplane processors - is a semiconductor IP licensor recognized by the Gartner Group as the fastest growing semiconductor IP supplier in 2008.  Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific dataplane performance targets. Tensilica's DPUs  power SOC designs at system OEMs and five out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.