Vitesse's New Forward Error Correction Technology Accelerates Migration to 100G

Breakthrough CI-BCH eFEC Offers Best-in-Class Net Electrical Coding Gain and Reduces Implementation Complexity for 100G Optical Systems

OFC/NFOEC 2010 - SAN DIEGO - March 22, 2010 - Vitesse Semiconductor Corporation (Pink Sheets: VTSS.PK), a leading provider of advanced IC solutions for Carrier and Enterprise networks, today announced immediate availability of its enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. Vitesse's new, patented Continuously Interleaved BCH (CI-BCH™) eFEC code offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in single FPGA form at 100G. Compared to today's FEC solutions, applying Vitesse's CI-BCH eFEC enables both 40G and 100G backbones to operate over 25-50% longer spans, respectively, with lower power, lower cost, and lower latency.

As service providers upgrade 10G metro and long-haul networks to 100G speed, optical signal-to-noise ratio (OSNR) rapidly degrades due to amplified spontaneous emission noise. Left uncompensated, this OSNR degradation results in unacceptable transmission error rates. Additionally, the complexity of implementation increases exponentially as data rates increase. Enhanced FEC is better able to correct the increased error rates and support error free delivery over longer distances.

“Carriers are deploying 40G and 100G because the economics make sense; these are no longer science projects. The 40G optical market grew rapidly during 2009, with port shipment roughly doubling every year when compared to the previous years,” according to Andrew Schmitt, directing analyst, optical, Infonetics Research. “Based on their strong technology and market position, vendors such as Vitesse should benefit from both 40G and 100G as each market evolves.”

Available for both FPGAs and ASICs, Vitesse's CI-BCH code is offered at 7% and 20% FEC overhead for 40G and 100G implementations, respectively. The 7% overhead version offers 9.35 dB net electrical coding gain (NECG). The 20% version provides up to 10.5 dB NECG. The CI version of a class of base codes called BCH represents a unique advance in FEC codes, with superior performance to any block codes offered to date. Vitesse’s CI-BCH is the industry’s first eFEC to solve the implementation complexity issues associated with higher data rates. Both versions of Vitesse's code deliver superior performance at the lowest latency and power dissipation, as well as the smallest gate count, compared to current FEC alternatives.

High-gain error correcting codes developed over the last two decades share the attribute that solving one base code word helps improve the ability to solve other base code words at intersecting bit locations. Prior to Vitesse's work, high-gain, block-style codes developed for FEC have not been able to fully utilize this “codeword helping codeword” phenomena. Vitesse's CI-BCH takes advantage of “codeword helping codeword” to improve coding gain while reducing the cost of hardware implementation significantly.

For latency sensitive applications, the design offers a variable latency decoder using a common encoder, allowing lower latency to be achieved at the expense of coding gain. The decoder additionally collects FEC-corrected error statistics.

Learn more about Vitesse's Optical Transport Solutions at www.vitesse.com/optical-transport.

Demonstrating 40G/100G Solutions at OFC/NFOEC 2010

Vitesse will showcase in Corporate Village room #2945, Hall D, a live demonstration of its CI-BCH eFEC solutions together with market leading module vendors, as well as its 40G/100G PHY chipsets at OFC/NFOEC 2010 Expo, March 23-25, 2010 in San Diego, Calif., at the San Diego Convention Center. Also during the conference, Vitesse will participate in the following panels and presentations:   

• Sunday, March 21 at 4:30 pm: “Beyond 10 Gb/s Passive Optical Networks…What's Next?”
• Monday, March 22, 8:00 am: Network Technologies for Large Data Centers
• Tuesday, March 23, 3:00 pm: “Continuously-Interleaved BCH (CI-BCH) FEC Delivers Best-in-Class NECG for 40G and 100G Metro Applications”
• Thursday, March 25, 10:00 am: “RSOA-based 10.3 Gbit/s WDM-PON with Pre-Amplification and Electronic Equalization."

In addition, Vitesse will showcase its 100G eFEC solution in the OIF Components Showcase at OIF booth #3041 along with eight other component and module companies. The OIF Components Showcase will display components, modules, FECs, and/or other hardware supporting the OIF Physical and Link Layer 100G projects focused on Integrated Photonics Transmitters and Receivers, Forward Error Correction, and Transponders.

About Vitesse

Vitesse designs, develops and markets a diverse portfolio of high-performance, cost-competitive semiconductor solutions for Carrier and Enterprise networks worldwide. Engineering excellence and dedicated customer service distinguish Vitesse as an industry leader in high-performance Ethernet LAN, WAN, and RAN, Ethernet-over-SONET/SDH, Optical Transport (OTN), and best-in-class Signal Integrity and Physical Layer products for Ethernet, Fibre Channel, Serial Attached SCSI, InfiniBand(r), Video, and PCI Express applications. Additional company and product information is available at www.vitesse.com.